Advanced PXI digital subsystems address semiconductor test applications

20 April 2015

The on-going challenge for today’s test engineers is to identify and create new test systems that can offer significantly lower test costs as well as address the need for configurable, flexible test solutions  that offer comparable features to proprietary ATE platforms at a much lower cost. 

Semiconductor test system solutions based on PXI products have made advancements in functionality and performance over the past 3 or 4 years both in the areas of digital and RF test. For digital and SoC test applications, PXI digital subsystems offer moderate to high channel count, integrated pin electronics that support PMU per pin capability, and software tools for migrating test vectors. However, existing PXI digital subsystems are largely limited to verifying DC and functional test characteristics of a device due to their limited timing engine capabilities. To fully meet the test requirements found in “big ATE”, a PXI based test system (and its digital subsystem) must also be capable of testing a device’s AC characteristics, e.g. setup and hold times – a capability that has not been easily achieved by the current generation of PXI instruments.  

To adequately address the capabilities and functionality found in proprietary big iron ATE digital instrumentation, the digital instrument must have a flexible and dynamic timing per pin or channel capability. Unlike existing 3U PXI digital I/O subsystems which employ a “singular” timing system which means all I/O channels are clocked with the same edge, a dynamic timing per pin system provides the flexibility to position data independently and dynamically on a per channel basis. Additionally, data formatting (e.g. non return to zero or return to zero, etc.) offers added flexibility when emulating complex bus timing or if testing for pulse width sensitivity. With these dynamic timing features and data formatting, a PXI-based test system can offer the test capabilities that are comparable to “big iron” ATE systems.  

Dynamic timing implies the ability to move edges anywhere within a test step with adequate resolution.  By employing a dynamic timing interpolator, drive / sense test vectors can be positioned anywhere within a test step with 1 ns or better resolution – not just on the vector clock’s edge boundary. This flexibility allows users to precisely create vector timing without resulting to workarounds such as oversampling, a technique which employs the use of multiple vectors in order to achieve even moderate edge placement resolution.  In addition, the ability to “dynamically” program a pin’s timing vastly simplifies the creation / execution of timing Shmoo plots, validation  / characterisation of a device’s AC parametrics, and offers easier conversion of WGL, STIL and VCD test vectors. Performing these tests with an instrument that supports only “static” timing per pin requires much longer test times and in some cases, the instrument’s capabilities may just not be adequate for the application.


The next generation of PXI digital instrumentation offers the capabilities and test features normally only found in proprietary ATE systems. With advent of these new, advanced digital subsystems, PXI –based semiconductor test solutions are now a reality, offering a full range of features and capabilities formerly only available in “big ATE”.

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