Partners introduce first 15Gbit/s HMC interface

25 June 2014

Xilinx and Pico Computing announce a 15Gbit/s Hybrid Memory Cube (HMC) interface for All Programmable UltraScale device.

Xilinx’s 20nm UltraScale devices support the full HMC bandwidth of four lanes, comprised of 64 transceivers running up to 15Gbit/s. Pico Computing’s HMC controller IP yields memory bandwidth and performance/W in a small, modular, scalable footprint.

The combined solution can be used to begin 15Gbit/s HMC designs in high performance computing, packet processing, waveform processing, and image and video processing.
According to Xilinx, the 20nm FPGAs are the only devices currently available that can support all four HMC lanes for memory bandwidth with additional transceivers for datapath and control signals.

Pico Computing’s HMC controller is parameterised to yield optimised system configurations to meet specific design objectives. The number of HMC links addressed, the number and width of internal ports, clock speeds, power, performance, area, and other parameters can be “dialed in” to yield precisely the performance required.

The Pico Computing HMC Controller IP and Ultrascale  FPGA family are available now.

Contact Details and Archive...

Print this page | E-mail this page