SAR ADC is presented at VLSI circuits symposium
11 June 2014
Imec will present an SAR ADC in 28nm digital CMOS which achieves a peak resolution of 70.7dB only 2.3mW.
The low power pipelined SAR (successive-approximation register) ADC in 28nm digital CMOS with record resolution, speed and power performance. It targets wireless receivers for next-generation software defined radio, including wireless standards such as LTE-advanced and the emerging generation of WiFi (IEEE802.11ac).
In a software defined radio, the ADC needs high speed, high resolution and high power efficiency in a dynamic solution, supporting high, as well as low bandwidth standards. The pipelined SAR ADC (developed by imec and Renesas Electronics) achieves a peak SNDR (signal to noise distortion ratio) of 70.7dB at a speed as high as 200MS/s while consuming only 2.3mW at 0.9V supply voltage. The implementation in 28nm digital CMOS adds to its area and power efficiency, and also supports digitalisation of the radio, says the research centre.
For future wireless technologies, developing software-defined radios that support high bandwidth and well as low bandwidth standards, the ADC design exploit advanced CMOS technologies, enabling scaling towards smaller technology nodes for a better performance of the ADC.
Interested companies have access to imec’s ADC designs by joining imec’s industrial affiliation program, or through IP licensing.
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