FPGAs act as ASIC companion chips

15 April 2014

The ECP5 family of FPGAs break the conventional cost, power and functional density rules, claims Lattice Semiconductor.

Designed for small-cell, microserver, broadband access, industrial video and other high-volume applications, the family challenges the rules of conventional FPGA approaches to deliver SerDes to add features and functions alongside those delivered by ASICs and ASSPs.
Achieving 40% lower cost than competing solutions, optimisations include small LUT4 based logic slices with enhanced routing architecture, dual-channel SerDes to save silicon real estate, and enhanced DSP blocks for up to 4x resource improvements.
In wireless and wireline applications, the family delivers an FPGA for enabling implementation of data path bridging and interfacing in a small, low-cost package, measuring 10x10mm package.
They also offer PCI Express side-band connectivity for microservers and can implement the entire image processing functionality in a device that consumes under 2W for industrial video cameras (illustrated).
According to the company, the  FPGA family is the only portfolio that enables 85k LUTs and SerDes in the compact packages, amounting to 2X the functional density of competing solutions. Smart ball depopulation further simplifies package integration with existing PCB technology and reducing overall system cost.
Enhancements leading to 30% lower total power than other FPGA solutions include stand-by mode operation of the individual blocks including SerDes, dynamic I/O bank controllers and reduced operating voltage. This enables single channel 3.25Gpit/s SerDes functions starting below 0.25W, and quad channel SerDes functions starting below 0.5W for supporting interface standards, including DDR3, LPDDR3, XGMII and 7:1 LVDS, PCI Express, Ethernet (XAUI, GbE, SGMII) and CPRI.
The family is supported in the Lattice Diamond Software Tool. Devices are available immediately with production-qualification scheduled for August 2014.

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