Next-generation Zynq multiprocessing architecture
03 March 2014
Xilinx’s UltraScale MP (multiprocessing) SoCs extend the FPGA and 3D IC architecture to enable heterogeneous multiprocessing.
At Embedded World, Xilinx introduced the architecture for next-generation Zynq UltraScale MPSoCs. It extends the company’s ASIC-class UltraScale FPGA and 3D IC architecture to enable heterogeneous multi-processing with ‘the right engines for the right tasks’.
The architecture provides processor scalability from 32 to 64bits with support for virtualisation, the combination of soft and hard engines for real-time control and graphics/video processing, waveform and packet processing, next-generation coherent interconnect and memory, advanced power management, and technology enhancements that deliver multi-level security, safety and reliability. The architecture is claimed to bring a new level in system performance and integration at lower system power by combining heterogeneous multi-processing with the fastest FinFETs in the industry; TSMC’s 16nm FinFET process.
The architectural elements are coupled with the Vivado Design Suite and abstract design environments to simplify programming and increase productivity. There are C, C++, and OpenCL based design abstractions, third party system level abstractions from Mathworks and National Instruments, and IP based design abstractions and automation. These environments are claimed to enable easy software migration from the defacto standard 28nm Zynq-7000 All Programmable SoCs. The new MPSoC architecture will be supported by the ecosystem of software, middleware, OS support, debuggers, IP tools, boards, and design services for Zynq devices.
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