Imec demonstrates strained germanium FinFETs

11 December 2013

At IEDM (IEEE International Electron Devices Meeting), imec unveils a functional strained Ge quantum-well channel pMOS FinFETs.

It is fabricated with a Si Fin replacement process on 300mm Si wafers. The device shows a possible evolution of the FinFET/trigate architecture for 7- and 5nm CMOS technologies.

Embedded SiGe source/drain has been a popular stressor to produce strained Si to enhance pMOS devices. As devices shrink, the volume to implement stressors in the source and drain has also been scaled back. This is especially pronounced with thin-body devices like FinFETs.

Growing compressively strained Ge-channels on relaxed SiGe buffer, has already proved a boost to channel mobility; it is also scalable. The use of a fin replacement process to fabricate the strained Ge channel device makes it especially attractive for co-integration with other devices on a common Silicon substrate. The reported strained Ge p-channel FinFETs on SiGe trench buffer achieved peak transconductance (gmSAT )values of 1.3mS/µm at VDS=-0.5V with good short channel control down to 60nm gate length. The transconductance to subthreshold slope ratio of the devices (gmSAT/SSSAT)is high compared to published relaxed Ge FinFET devices.

Future developments will focus on improving the device performance through P-doping in the SiGe, optimising Si cap passivation thickness on the Ge, and improving the gate wrap of the channel.  The work provides a breakthrough in that it demonstrates a Ge-SiGe heterostructure-based quantum-well device in a FinFET form, which not only provides strain benefits but also enhances short-channel control. 

Implementing Ge into the channel through fin replacement process, is a key step to creating process possibilities for monolithic heterogeneous integration to extend CMOS and SOCs.

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