First 20nm architecture could double system performance

23 July 2013

First 20nm architecture could double system performance
First 20nm architecture could double system performance

Xilinx tapes-out the first 20nm All Programmable device and the industry’s first 20nm ASIC-class programmable architecture.

Two industry firsts at 20nm are being claimed by Xilinx. The company has taped out the first 20nm device, and the first 20nm All Programmable PLD. It has also implemented the industry’s first ASIC-class programmable architecture, UltraScale.

The company believes that it is the equivalent to a generation ahead of its competitors to delivering 1.5 to two times more realisable system-level performance and integration.

The UltraScale architecture was developed to scale from 20nm planar, through 16nm and beyond FinFET technologies, and from monolithic through to 3D ICs. It not addresses the limitations to scalability of system throughput and latency, but directly addresses the obstacle to chip performance at advanced nodes: the interconnect, says the company.
The architecture manages multi-hundred Gbit/s levels of system performance with smart processing at full line rate, scaling to terabits and teraflops. As well as increasing the performance of each transistor or system block, or to scale the number of blocks in the system, the objective is to fundamentally improve the communication, clocking, critical paths, and interconnect to address the data flow and real-time packet, DSP, and/or image processing.

The programmable architecure optimises the data flow for wide buses that support multi-terabit throughput, says the company and uses multi-region ASIC-like clocking, power management, and next-generation security

There are also optimised critical paths and built-in high-speed memory, cascading to remove bottlenecks in DSP and packet processing. Other features are step function in inter-die bandwidth for second generation 3D IC systems integration and I/O and memory bandwidth with “dramatic” latency reduction and 3D IC wide memory-optimized interface, says the company.

Routing congestion is eliminated and the company’s Vivado tools are claimed to result in at least 90 per cent device utilisation without degradation in performance.

Initial UltraScale devices will extend the company’s Virtex and Kintex FPGA and 3D IC families now based on 28nm process technology, and will serve as the foundation for future Zynq UltraScale All Programmable SoCs

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