PCI Express timing devices

24 January 2012

Silicon Laboratories has announced the expansion of its PCI Express (PCIe) clock generator and clock buffer portfolio
Silicon Laboratories has announced the expansion of its PCI Express (PCIe) clock generator and clock buffer portfolio

Silicon Laboratories has announced the expansion of its PCI Express (PCIe) clock generator and clock buffer portfolio.

This now provides the industry’s broadest range of clocking solutions to address the stringent specifications of the PCIe Generation 1/2/3 standards. Silicon Labs’ expanded PCIe timing portfolio includes both off-the-shelf Si5214x clock generators and Si5315x clock buffers for power- and cost-sensitive PCIe applications and the Si5335 web-customisable clock generator/buffer for FPGA and SoC-based designs requiring various differential clock formats that also comply with the PCIe standard.

The PCIe interconnect standard has been widely adopted in numerous applications including consumer electronics, blade servers, storage, embedded computing, IP gateways and industrial systems. The PCIe interface is also supported in FPGA and SoC devices, providing designers with versatile, high-performance solutions for transferring data within systems. Silicon Labs has applied its patented mixed-signal technology to deliver a suite of flexible clocking solutions that enable PCIe design across varying market and application requirements.

“By applying our ‘one-stop-shop’ timing IC supplier model to the PCIe market, we’re providing customers with the utmost flexibility in choosing the right clocking solutions for their PCIe application needs,” said Mike Petrowski, General Manager of Silicon Labs’ timing products. “Our expanded PCIe timing solution portfolio gives developers a full complement of off-the-shelf options for minimising power, enhancing signal integrity and reducing cost, as well as the industry’s most customisable clock generators and buffers for FPGA-based designs.”

The Si5214x clock generator and Si5315x clock buffer families consist of two to nine-output timing devices that offer the industry’s highest level of performance per watt. The new PCIe clock generators and buffers are twice as power efficient as competing clocking solutions. Lower power helps minimise heat dissipation and reduces the need for additional cooling components and power regulators. The devices also meet PCIe jitter requirements with up to 50% margin, leading to better system reliability and enhanced bit-error-rate performance.

Further easing design complexity, the Si5214x and Si5315x devices use output buffer technology to integrate all external termination resistors, thereby reducing component count, BOM cost, board space and power. The smallest PCIe clocking devices on the market, the new clock generators and buffers are ideal for space-constrained applications.

To combat electromagnetic interference (EMI) and radio frequency interference (RFI), the Si5214x and Si5315x families feature programmable edge rate and skew controls for each individual output. Using a built-in I2C interface, developers can fine-tune signals and fix integrity issues on the fly without adding more components. This signal integrity tuning capability streamlines EMI compliance, speeding time to market for PCIe board designs.

The Si5335 clock generator/buffer IC is the industry’s easiest-to-customise clocking solution for addressing complex timing challenges in PCIe- and FPGA-based applications. Factory-customised, pin-controlled Si5335 devices are available in two weeks (without minimum order restrictions) through Silicon Labs’ easy-to-use ClockBuilder Web configuration. Any combination of up to four output frequencies ranging from 1 to 350 MHz can be configured on the Si5335 outputs. Up to three unique device configurations can be specified for a single part number, enabling the Si5335 to replace three separate clock generators or buffers and allowing developers to reuse a custom Si5335 device across multiple designs.

The Si5335 clock generator/buffer IC features up to five user-assignable control pins to simplify PCIe and FPGA-based system design and streamline EMI compliance with its PCIe-compliant spread spectrum clocking option. The Si5335 device features Silicon Labs’ patented MultiSynth fractional divider technology, which enables any-frequency synthesis on every output clock with sub-picosecond jitter. The Si5335 exceeds the performance requirements of PCIe, Ethernet and mass storage industry standards. Its 0.45 ps maximum (rms) jitter is more than twice as low as the PCIe 3.0 jitter requirement (1 ps).

The Si5335 simplifies multi-chip-clocking challenges by supporting any combination of differential formats such as LVPECL, LVDS and CML and single-ended formats like LVCMOS. Eliminating the need for multiple clock generators and/or buffers, the device’s outputs support any combination of four differential outputs or up to eight LVCMOS outputs. This output format flexibility makes it easy for designers to accommodate the widely varying output signal formats and power supply voltages common in PCIe-, FPGA- and SoC-based embedded systems.

Production quantities of Silicon Labs’ latest PCIe clock generator and buffer ICs are available now in a wide range of small-footprint packages.

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