Addressing productivity crisis for SoC design

11 May 2010

Cadence Design Systems has released Cadence Encounter Digital Implementation (EDI) System 9.1
Cadence Design Systems has released Cadence Encounter Digital Implementation (EDI) System 9.1

Cadence Design Systems has released Cadence Encounter Digital Implementation (EDI) System 9.1.

This is a complete and integrated digital design, implementation, and verification environment for the development of large-scale, complex SoCs. The new and expanded suite of capabilities in EDI System 9.1 answers the industry call for improved designer productivity in developing advanced low power and mixed signal SoCs at leading-edge process nodes, such as 32 and 28 nanometer, with millions of gates, including hundreds of IP elements and embedded processors.

Consumer demand for smaller, faster, feature-rich devices drives demand for larger-scale, higher-performance and lower-power SoCs. To compete in these markets, semiconductor companies must deliver the best and most differentiated designs, faster than the competition; a tricky combination that forces semiconductor companies to work through conflicting design objectives and sometimes incur higher manufacturing costs or take on greater technology and business risks.

EDI System 9.1 removes these challenges to design productivity through innovative design exploration capabilities. By combining automatic floorplan synthesis, unique data abstraction modelling, and new concurrent macro and standard cell placement, all fully driven by the embedded signoff analysis capabilities of EDI System, users can quickly find and implement the optimal physical architecture of a chip.

Design exploration does this by automatically and concurrently examining thousands of combinations of design variables, option settings, floorplan architectures, and physical implementation approaches in parallel. This examination allows users to fully explore the range of design possibilities, and deliver smaller, faster, higher functioning chips, while accelerating design schedules by weeks or months.

EDI System also improves designer productivity by broadening its integrated suite of native sign-off capabilities. Building on its existing foundry certified power, timing, and signal integrity (SI) sign-off capabilities, EDI System 9.1 now adds silicon-accurate extraction and design-for-manufacturing (DFM) analyses to complete the picture.

The new integrated, turbo QRC extraction capability provides fast in-design, incremental sign-off extraction and drives fast and convergent design closure for physical and electrical design requirements. Also, since foundries now mandate DFM checks in the physical design flow at 40 nanometer and below, built-in, foundry-certified DFM analysis is a must-have at these nodes. The integrated DFM capability, Turbo Litho Physical Analyser, brings built-in litho pattern intelligence and filtering to the interconnect routing phase, enabling automatic detection, prevention, and correction of potential litho hotspots before they happen. This capability improves DFM and yield for advanced 40, 32 and 28 nanometer nodes and is significantly faster than traditional lithography sign-off tools.

EDI System 9.1 also extends its memory architecture to achieve significant gains in memory capacity, acceleration in single-CPU operations, and improved performance scalability across its multi-CPU backplane, bringing efficient parallel processing throughout the design flow.

The convergence of design exploration, sign-off-driven implementation, faster performance, and larger capacity in EDI System 9.1 has a significant impact to designer productivity. It enables designers to design, implement, and verify chips 2-3 times larger and two times faster than traditional flows and with superior quality of silicon. The tight integration of sign-off checks in the implementation phase enables exceptional correlation to final silicon, thereby reducing the potential for expensive silicon re-spins.

“Our 10GBASE-T PHYs are tuned for the highest performance and lowest power on the smallest die area,” said Sridhar Begur, Vice President of engineering at Teranetics. “With EDI System’s end-to-end multi-CPU timing closure solution, we were able to reduce our turnaround time by more than half, and meet our design objectives significantly ahead of schedule. EDI System also provided us with an advanced 40 nanometer flow, enabling accurate, in-design prevention and fixing of lithography effects that translated to increased manufacturability and yield of our designs.”

The constant pursuit of excellence in semiconductor design leads to a stream of technology advancements and fundamental shifts in design methodologies and processes to better manage SoC complexity, improve quality of silicon, and to ensure chips get to market on time. Silicon-on-insulator (SOI), high-k metal gates, and 3D-IC/through-silicon via (TSV) are just a few examples of some of these shifts taking place. In addition, a growing list of advanced low power design techniques such as dual flip-flop, pulse latch, power switch optimisation and hierarchical low power design are being explored and employed by companies seeking the utmost in power reduction. Cadence, in collaboration with leading semiconductor companies and ecosystem partners, continues to play a pivotal role in driving the definition, development, and enablement for these areas, and EDI System 9.1 is a prime example of where it all comes together.

“Semiconductor leaders and ecosystem partners provide us with early insight into emerging challenges, and this collaboration is exactly what allows us to get ahead of the curve,” said David Desharnais, Group Director of Design, Implementation and Verification Product Management at Cadence. “The compounding complexities of chip design and the economics associated with bringing a SoC to market drive a renewed interest in closing the productivity gap and achieving chip profitability as quickly as possible. The new EDI System 9.1 release provides the industry with the capability to achieve those goals.”

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