Efficient clocking solutions for high-speed serial interface designs

29 March 2010

Designers of digital systems face new challenges as high speed serial interfaces, using Serialised/Deserialiser (SERDES) technology, replace the more traditional parallel bus architectures. One odf these challenges is with the clocking device. Srirama Chandra discusses a new option.

SERDES-based designs increase bandwidth while reducing signal count, bringing a host of advantages such as lower routing congestion, reduced switching noise, lower power and lower package costs. The main disadvantage of SERDES technology is the need for very precise, ultra-low jitter components to provide the reference clock required to control the high data rate serial signals. Even with tightly controlled component placement, short signal lengths and signal routing constraints, the jitter budget in these interfaces can be very tight.

Fixed frequency oscillators are available for many of the common SERDES standards; however, these solutions are very expensive. In addition, this approach lacks flexibility and can make debugging, testing and manufacture difficult.

An alternative solution is to use programmable clock devices, like those in the Lattice ispClock family, and a low-cost CMOS oscillator. The ispClock devices can satisfy a range of SERDES clock requirements with ultra-low jitter, while retaining the flexibility provided by a user programmable device. This article will explain how programmable clocking devices can be used to more efficiently implement a variety of reference clocking sub-systems for SERDES-based interfaces. A sample XAUI application will be examined in detail.

SERDES Reference Clock Source Challenges
Selecting a reference clock source for any SERDES-based protocol, whether implemented in an FPGA, SoC or ASSP, is very challenging. Device cost, minimisation of noise generated via coupling of high-speed signals, ultra-low jitter requirements, routing constraints due to signal length matching requirements, careful power supply design (including noise considerations, limitations on component placement, signal routing requirements and power rail decoupling), as well as testing/manufacturing requirements must all be taken into account and various trade-offs analysed.

The traditional approach to driving a SERDES reference clock is with a true differential output oscillator fixed at the correct frequency and chosen specifically for low jitter and phase noise. This solution can be very expensive, and is not flexible enough to be re-used in subsequent designs. Fixed solutions, by their very nature, are also limited in flexibility, and a clocking system design for one interface can’t be easily used in a new design. Instead, the new design must be started over from the beginning and will need a different device, different architecture and perhaps a new set of placement, layout and routing guidelines. Stocking, testing and manufacturing are more complicated as well: fixed frequency devices require the stocking of multiple devices for different standards, increasing manufacturing expense. Testing as well can be more difficult if devices lack the ability to change frequencies or sweep clock output ranges for sub-system test and debug.

The technology used in fixed-frequency low-jitter differential oscillators typically does not include internal PLLs to generate the output frequency, so these devices can have noisy sidebands and multi-modal distributions when analysed in the frequency domain. Challenges also exist in finding the ideal termination and differential I/O logic standards and maintaining quiet power to the source. These oscillators may cost between $12 to $50 depending on specifications, quantity, packaging and temperature ranges.

An emerging class of programmable logic devices, like the ispCLOCK 5406D from Lattice Semiconductor, provides a flexible, ultra-low jitter, low-cost solution to driving SERDES reference clocks. These devices and a low-cost CMOS oscillator are capable of meeting the stringent ultra-low jitter requirements of FPGA, SoC and ASSP SERDES reference clocks.

In addition, this enhanced implementation keeps device cost low and simplifies design, test and manufacturing. Because these devices are programmable, it is possible to re-use a design by just programming a different function for the clock. For example, outputs may be changed from one standard to another - perhaps from LVDS to LVPECL -- when replacing expensive crystals with different interfaces. An ispClock -based design can be used over multiple future designs to improve time to market, reduce inventory and simplify manufacturing. Functional changes can even be made in the field to simplify fixes, implement upgrades and improve quality of service. Because these clock devices have multiple outputs with individual phase and time skew, edges can be “swept” over a wide range of testing to better determine limitations on component tolerances for a much more robust system.

An example system using a low-cost oscillator and an ispClock5400D device is shown in Figure 1. The oscillator is decoupled and isolated from power supply noise by using a few capacitors and ferrite beads. The single-ended oscillator output is used in conjunction with a voltage divider to create a differential signal for the reference input on clock device. By routing the reference signals close together, common mode noise can be minimised, improving signal integrity.

Using the ispClock5406D for a XAUI Reference Clock
A common SERDES application is found in a XAUI design. A XAUI SERDES runs at 3.125 GHz and has a stringent jitter requirement of 0.35 UI (Unit Intervals), a UI being the full period of the waveform. (At 3.125 GHz the full period is 1/3.125 GHz or 320 ps. A UI of 0.35 at 320 ps is thus 120 ps). A common approach to creating the on-chip 3.125 GHz SERDES clock is to use a precise input reference clock at 1/10 of the SERDES rate, or 312.5 MHz. The reference clock must be precise enough to allow the SERDES design to meet the stringent jitter requirements of the XAUI specification.

The isp5406D is easily configured via GUI-based design software (Lattice PAC-Designer 5.2). The GUI for configuring the ispClock5406D is shown in Figure 2. The block diagram of the device is used to define the various configuration options. The user simply double clicks on the function in the block diagram and a dialogue box opens, showing the various programmable options for that function. For example, in the dialogue box in the upper right the user enters the reference clock frequency and feedback signal source.

As shown in Figure 2, the clock reference input sources for the Loop-Filter and VCO block can be selected from either the REFA or REFB differential inputs. This block’s output is used by the Output V-Divider block to generate four frequencies divided down from that generated by the PLL (divide-by 2, 4, 8 and 16). The feedback signal, either from the Output V-Divider block or the FBK input for external feedback, provides the reference clock to be “matched” by the VCO. If a high divisor signal from the Output V-Divider block is selected for matching to the input reference clock, the lower divisor outputs will be multiples of the feedback signal, creating an effective multiple of the reference clock. In this example, with a 78.125 MHz input reference clock sourced on REFA and a V-Divider from the divide-by-eight output being fed back, the divide by-eight output will be 78.125 MHz, the divide-by-four output will be 156.25 MHz and the divide-by-two output will be 312.5 MHz.

The output frequencies generated by the V-divider are available to the routing matrix and can be assigned to any of the isp5406D outputs. Each output has a separate phase and time skew setting that can be applied to adjust the outputs for routing delays and other detailed timing considerations. Finally, the type of output can be selected from any of M-LVDS, LVDS, LVPECL, HCSL x6, HSTL/eHSTL, SSTL 1.5 V/SSTL 1.8 V or SSTL 2.5 V. In the example design the 312.5 MHz and 156.25 MHz signals are made available on the BANK_0 thru BANK_3 outputs- as both LVDS and LVPECL. REFB is also selected for use as an output on Bank 4 and Bank 5. This could be for a separate clock signal which needs some slight timing adjustment.

XAUI Test System Results
A test system was created using the ispClock 5406D evaluation board and a LatticeECP3 FPGA development board. The block diagram of this test set-up is shown in Figure 3 and is superimposed on the picture of the boards used in the design, with the ispClock5406D board on the left and the ECP3 FPGA board on the right. (Note that the clock signal between the boards uses SMA cables. This is a more challenging signaling environment than that used for an integrated clocking solution.)

An Epson CMOS oscillator, operating at 78.125 MHz, was used as the reference clock for the ispClock 5406D. The ispClock 5406D is programmed to multiply the reference frequency by four to create a 312.5 MHz clock in the XAUI design implemented with the LatticeECP3 FPGA. The ultra-low jitter 312.5 MHz reference clock is multiplied by 10, using the on-chip ECP3’s CDR/PLL block. The 3.125 GHz clock is distributed to the high-speed portions of the XAUI function: SERDES receive (RX) and transmit (TX) paths as well as the 8b10b Decode and Encode blocks.

During jitter testing the XAUI State Machine is programmed to output the standard PRBS7 test pattern. This shows up on the TX Path output and the DOUT+/- signals, illustrated at the bottom of the LatticeECP3 FPGA block in Figure 3. These outputs are connected to an Agilent DSO-81304B scope to capture detailed jitter data. Figure 4 displays the key results in graphical form for the measurements made at 0oC. Similar measurements were made at -55oC and +85oC. The table at the bottom of Figure 4 shows the results of the key jitter measurements during testing. The Total Jitter measurement, which needs to meet the 120 ps (0.35 UI) requirement of XAUI, is seen to be a worst case of 105.65 ps and 0.33 UI over the temperature range of -55oC to +85oC. Again, these compliant results were achieved using two separate boards. A single board implementation should produce even lower jitter results.

The configuration of the ispClock 5406D is held in on-chip, non-volatile memory that is reprogrammable through a JTAG interface. Many functions of the device can also be modified “on-the-fly” via the I2C interface. The programmable features of an ispClock 5406D-based system support a variety of additional functions, including TH and TCO timing margin measurements to help test the robustness of a design; margin testing with independently skewed clocks between send and receive channels to improve manufacturability; and precise alignment of a clock at the centre of the data valid window for improved system reliability.

Srirama Chandra works for Lattice Semiconductor Corporation


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