Low power, low cost RRH solution

18 November 2009

Lattice Semi and Affarii have developed a 3G/4G-based Remote Radio Head (RRH) solution
Lattice Semi and Affarii have developed a 3G/4G-based Remote Radio Head (RRH) solution

Lattice Semi and Affarii have developed a 3G/4G-based Remote Radio Head (RRH) solution.

This is the first time a full RRH solution has been made available using low power, low cost FPGAs that allows low power RRHs to be deployed without sacrificing flexibility or performance.

Traditionally, near antenna logic for MIMO-based RRH systems has been implemented in high end, premium FPGAs. The high cost and power dissipation of these high end FPGAs has forced vendors to sacrifice design flexibility and attempt expensive ASIC conversions. However, the combination of the industry leading low cost, low power LatticeECP3 FPGA and Affarii’s digitalTRX technology provides an unprecedented RRH solution that includes Digital Up/Down Converter (DUC/DDC), Crest Factor Reduction (CFR) and Digital Pre-Distortion (DPD) functionality. Additionally, Lattice provides CPRI/OBSAI and Ethernet technology implemented on the ECP3 FPGA’s low cost 3G SERDES transceivers.

A fully integrated RRH solution is now available, providing baseband processing for up to two transmit and four receive antennas on a single silicon device, with each antenna supporting four carriers and 20MHz of modulation bandwidth. When used with industry standard Doherty amplifiers, the Digital Predistortion provides up to 30dB of ACLR correction per transmit antenna with PA output efficiencies exceeding 40%. The solution is fully customisable, with end applications including WCDMA, LTE, WiMAX, WiBro, TD-SCDMA and DVB-T/S/H.

The RRH solution is supported by a comprehensive development and test environment that includes GUI-based design simulation, performance analysis and a production test API with design examples. An in-circuit hardware development platform is also being developed.

“The rapid evolution of the wireless infrastructure marketplace means designers must continuously adapt to changing product requirements,” said Shane Flint, Managing Director of Affarii Technologies. “Our digitalTRX technology provides DPD and CFR solutions that offer a fast, flexible and cost effective platform for digital transceiver and RRH development. With high ACLR correction and low dynamic power consumption per antenna, designers get both industry leading performance and the flexibility to create the solutions they want.”

Shakeel Peera, Lattice’s Marketing Director for SRAM FPGAs, added: “Our mid-range LatticeECP3 FPGA family offers our customers an unprecedented combination of low power, high value and the features and performance necessary for sophisticated wireless RRH applications. We are pleased to partner with Affarii to showcase the versatility of the ECP3 FPGA in providing low cost solutions for near antenna logic.”

The mid-range LatticeECP3 FPGA family is comprised of five devices that offer standards-compliant multi-protocol 3G SERDES, DDR1/2/3 memory interfaces and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing. Toggling at 1Gbps, the LatticeECP3 FPGAs also feature the fastest LVDS I/O available in a mid-range FPGA family, as well as embedded memory of up to 6.8Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O. The LatticeECP3 FPGA family's high performance features include:
• 3.2Gbps SERDES with the ability to mix and match multiple protocols including CPRI, OBSAI, XAUI, Serial RapidIO, PCI Express, 10GbE and SGMII/Gigabit Ethernet on each SERDES quad.
• The SERDES/PCS blocks have been designed specifically to enable the design of the low latency variation CPRI links that are found in wireless basestations with Remote Radio Head connectivity.
• DSP blocks allowing up to 36x36 Multiply and Accumulate functions running at >400MHz. The DSP slices also feature innovative cascadability for implementing wide ALU and adder tree functions without the performance bottlenecks of FPGA logic.
• 1Gbps LVDS I/O, with Input Delay blocks, allows interfacing to high performance ADCs and DACs.

With these features, the LatticeECP3 FPGA solution is ideally suited for deployment in high volume cost and power-sensitive wireless RRH infrastructure equipment.

Contact Details and Archive...

Print this page | E-mail this page

This website uses cookies primarily for visitor analytics. Certain pages will ask you to fill in contact details to receive additional information. On these pages you have the option of having the site log your details for future visits. Indicating you want the site to remember your details will place a cookie on your device. To view our full cookie policy, please click here. You can also view it at any time by going to our Contact Us page.