Improved design productivity
23 October 2009
M-language and model-based solution delivers up to 10x higher productivity
M-language and model-based solution delivers up to 10x higher productivity.
Synopsys has introduced its Synphony HLS (High Level Synthesis) solution that integrates M-language and model-based synthesis to deliver up to 10x higher design and verification productivity than traditional RTL flows for communications and multimedia applications.
Synphony HLS creates optimised RTL for ASIC and FPGA implementation, architecture exploration and rapid prototyping. In addition, Synphony HLS complements C/C++ based flows by generating C-models for system validation and early software development in virtual platforms. Synphony HLS integrates with Synopsys’ Design Compiler, Synplify Premier, Confirma, VCS, System Studio and Innovator products to deliver the most comprehensive prototyping, implementation and verification flows from algorithm to silicon.
The Synphony HLS delivers significantly higher productivity than traditional methods by providing benefits such as an automated flow from M to optimised RTL, synthesis of optimised RTL architectures for ASIC and FPGA, rapid prototyping methodology for early algorithm validation, C-model generation for early software development and fast system validation, and unified verification across multiple flows including prototyping and ASIC implementation.
The Mathworks’ MATLAB environment has been broadly adopted for algorithm exploration and design because it allows concise expression of behaviour at an extremely high level of abstraction. The M-language models developed in this environment are typically re-coded and re-verified at the RT Level (RTL) and in some cases in C/C++ for implementation and verification. Unlike inefficient and error-prone manual re-coding flows, Synphony HLS creates implementable RTL and C-models directly from high-level M-language code and the Synphony HLS-optimised IP model libraries. Using a unique constraint-driven fixed-point propagation feature, designers can quickly and intuitively derive fixed-point models from a synthesisable subset of high-level, floating-point M-code. The Synphony HLS engine will then synthesise architecturally optimised RTL to meet area, speed and power goals. Synphony HLS allows designers to stay in their preferred algorithm modeling language, eliminating the need to re-code and re-verify models and enabling early system-level validation and verification.
The Synphony HLS engine can synthesise optimised architectures for ASIC, FPGA, rapid prototyping or virtual platforms while maintaining coherent verification through all levels of the implementation flow. Given the user-specified target and architectural constraints, the HLS engine automatically optimises at multiple levels by applying pipelining, scheduling and binding optimisations across language and model boundaries, including M-language, IP blocks and throughout the design hierarchy. Furthermore, Synphony HLS includes a new advanced timing estimation capability that automatically utilises Design Compiler for accurate information needed in automatic pipelining and rapid timing closure for a given ASIC technology. It includes advanced timing and device-specific optimisations for a broad range of FPGA families from Actel, Altera, Lattice and Xilinx. This includes optimised mapping to hardware multipliers, memories, shift registers and other advanced hardware resources in today’s FPGA devices.
With Synphony HLS and Synopsys’ technology-leading Confirma rapid prototyping solutions, design teams can quickly create a pre-silicon prototype of their design and start high-performance algorithm validation and software development much earlier in the design cycle. Synphony HLS complements C/C++ implementation, verification and embedded software development flows by making C-model creation a natural byproduct of the development flow. It generates fixed-point ANSI-C models that can be used in a variety of system simulation environments and virtual platforms including Synopsys’ Innovator, System Studio, VCS and SystemC flows. Thus Synphony HLS enables C-based verification and validation to start much earlier in the design cycle.
“Until now, there has not been an automated way to derive a coherent verification flow across abstraction levels nor an implementation flow with optimised output from the very popular M language,” said Gary Meyers, Vice President and General Manager of the Synplicity Business Group at Synopsys. “With Synphony HLS, we can provide a faster and more reliable path to system and software validation than competing solutions. Combined with Synopsys’ technology-leading system prototyping and hardware-assisted verification solutions, design teams can more economically and more reliably design and verify their complex chips and software.”
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