Evolution in embedded: system-level programmability

20 October 2009

PSoC 3 Architecture Block Diagram
PSoC 3 Architecture Block Diagram

In this article, Jim Davis explores the embedded design challenges engineers face on a day-to-day basis and, in a pragmatic manner, discuss how these challenges can be overcome with true system-level programmability.

How many embedded projects have successfully transitioned between lifecycle phases of the project without major rework of system designs, bill of materials or layouts? If the answer is less than 100%, as the majority of the embedded world is, then a new methodology to embedded design that will save the engineer countless hours, dollars and headaches would be the perfect solution. This solution is based on true system-level programmability.

But first, what is true system-level programmability?

There are three sections which need to be recognised, from right-to-left: Programmability, System-Level, and True. Programmability is not to be confused with configurability; programmability is the ability to build a function using basic building blocks. In this context, these basic building blocks are implemented in hardware and are used together to build a function by means of configuring registers, data-paths and signal-paths. For example, figure 1 below describes the basic building blocks within Cypress’s next generation PSoC device architectures, PSoC 3 and PSoC 5, for implementing true system-level programmability. These basic building blocks, as highlighted in the figure, consist of a high performance 8-bit 8051 (PSoC 3) or 32-bit ARM Cortex M-3 (PSoC 5) processor, a programmable clocking tree, Universal Digital Blocks (UDBs), programmable analogue blocks and programmable routing and interconnects (analogue, digital and system buses).

The clocking system of these architectures enables a programmable set of analogue and digital clocks to support a variety of peripherals such as ADCs, PWMs, counters, etc. With eight individually sourced 16-bit clock dividers for the digital system peripherals and four individually sourced 16-bit clock dividers for the analogue system peripherals all reaching back to a set of four internal or two external clock sources, the architectures have a powerful clocking tree.

A UDB is a very powerful, flexible digital logic block. Each UDB in the architectures contain an ALU-based 8-bit datapath, two fine-grained PLDs, a control and status module - as well as a clock and reset module. These elements can be combined to perform the function of a low-end microcontroller; they can also be chained together with other UDBs to enable larger functions. Alternatively, they can implement digital peripherals such as timers, counters, PWMs, UARTs, I2C, SPI, and CRCs. With 24 UDBs in some PSoC 3 and PSoC 5 families of devices, you can even implement a 24-core processor in addition to the 8051 or ARM Cortex-M3 processors, or the internal DMA — a very powerful architecture.

The analogue capabilities of these solutions combine high-precision fixed-function analogue (reference voltage accurate to +/- 0.1% over industrial temperature and voltage ranges) with a set of programmable analogue peripherals that can be used to implement: mixers, trans-impedance amplifiers, buffers, op-amps, and more. The combination of flexible, high-precision analogue capabilities opens up many possibilities for unique, powerful designs.

The routing and interconnect of this architecture, as you can see in figure 1, is made up of system buses that enable any GPIO to be digital, analogue, CapSense, or LCD drive I/O — a truly powerful feature that can offer significant cost savings (4-layer to 2-layer PCBs) and easier board layout with true routing freedom.

So, what does true system-level programmability mean? We have long had component-level programmability in the form of programmable digital logic (CPLDs, FPGAs, etc.), programmable analogue (switched-capacitor and similar functions), programmable clocks and programmable processors. What system-level programmability means is simply all of these programmable components in a single platform, a single device all controlled and configured via an easy to use, hierarchical schematic-based, software development environment. An example of this can be seen in Figure 2, this shows a system-level view of a brushless DC motor control application. As you can see in this figure, you don’t need to worry about the details of how these individual components are instantiated; instead the focus is on what you want these peripheral functions to do. Whether it’s taking tachometer, temperature or pump pressure readings to provide a feedback loop to the motor control function, or driving the 3-phase motor using individual PWM controls, PSoC provides the solution to system design challenges without worrying about the low-level details of which discrete ICs or peripheral components to use.

Finally, true system-level programmability should be distinguished from devices that feature configurable fixed-function peripherals. It implies that if a certain function is not needed, the resources that are assigned to it for other purposes can be used. This saves the waste of functionality in a device, because a certain function has been avoided. The only wasted space, if any, on the device is comprised of basic building blocks, ready to be used to enact changes in your designs or implement additional functionality.

Pragmatic application to solve embedded design challenges
When designing in the embedded space, the engineer can face many design challenges. First is the ability to adapt to change. These changes can often occur in the requirements, layouts, designs, or availability of materials. Second is getting the product to market, and quickly beating the competition and releasing a product at the right time to net the most impact. Another common challenge is analogue complexities—choosing, configuring and using the right parts for the right purposes. The ability to protect your design IP is paramount; this can prevent any design replications, which is of importance to any individual or company. Cypress’s programmable system-on-chip and development software has been designed to meet these problems head-on, by addressing these challenges.

Adapting to Change
The only constant in the life of an embedded engineer is change, and their ability to embrace change by planning for it, and using tools that empower them to adapt, is the only way they can truly be successful. As figure 2 demonstrates, a change to an engineer working with a programmable system on chip involves a simple modification of a peripheral — perhaps increasing an ADC’s resolution, or it could be as complicated as adding additional functionality into a design, like a control interface via USB or an LCD Segment Display and capacitive sensing buttons (figure 3). With true system-level programmability engineers can embrace change and use it to develop the best products they can imagine.

The biggest challenge in getting to market quickly is not always by concepts or ideas, but in creating a product from these ideas. Bringing a product to market quickly can earn higher margins and a more focused market with less competition. Programmable engineering enables rapid-prototyping of a solution with easy in-chip tweaking, and the ability to program with a system-level software development environment. With these two capabilities, you can easily design a hardware solution to understand the true requirements and get your product into production.

Analogue Complexities
The programmable system-on-chip platform and its software development environment ease the use of analogue circuitry and functions through its intuitive system-level, schematic-based design methodology. As figure 2 shows, the instantiation of analogue peripherals is as simple as a drag-and-drop of the component on to the design canvas in an easy-to-use environment, in this case using Cypress’ PSoC Creator, followed by peripheral configuration settings specific to the function being implemented. In figure 2, the configuration of the ADC includes modifying the resolution, conversion rates, or clock sources. The instantiation of other analogue peripherals like trans-impedance amplifiers, filters, analogue multiplexers, comparators, DACs and other peripherals is just as simple.

The programmable system-on-chip architecture provides an additional layer of security by its system-level programmability, which is embedded in the device. If a competitor examines the die, all that can be found are the components that make up the device itself, and not the firmware that initialises the system developed using the software. The firmware stored in the PSoC device is defined by memory block to accommodate several levels of protection across the entire device. Using this level of secure programming can safeguard designs when implemented in the programmable system-on-chip device, which can quite easily defend against any standard reverse engineering techniques.

Cypress’s PSoC programmable system-on-chip and its development software unleash true system-level programmability with its new PSoC 3 and PSoC 5 architectures to help engineers easily overcome everyday embedded design challenges and allow the focus to be on what really matters: the product. These new architectures extend the world’s only programmable embedded design platform, removing many of the design limitations. In one chip, it is possible to take advantage of high-precision programmable analogue including 12- to 20-bit delta-sigma ADCs, a digital logic library with dozens of drop-in peripherals, best-in-class power management and rich connectivity resources; all with an integrated high-performance, single-cycle 8051 or advanced ARM Cortex-M3 processor in the PSoC 3 or PSoC 5 architectures, respectively.

Jim Davis works for Cypress Semiconductor Corp

PSoC 3 Architecture Block Diagram

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