Solve the routing bottleneck

20 July 2009

Hitachi’s deployment of Allegro Global Route Environment technology streamlines PCB design process.
Hitachi’s deployment of Allegro Global Route Environment technology streamlines PCB design process.

Hitachi cuts place-and-route design time by 40% using Cadence design software for PCBs.

To reduce their Printed Circuit Board (PCB) place-and-route design time by 40% for a high-speed communication product, Hitachi used Cadence’s Allegro PCB design that uses the Global Route Environment (GRE) technology.

Hitachi applied the GRE place-and-route design methodology to its PCB place-and-route from interconnect planning to complete routing, with full constraints for high-speed digital signals where no automation was previously available. “High-speed PCBs require significant enhancements in performance, and gigahertz-level signals are becoming common,” said Toru Hiyama, general manager, MONOZUKURI Innovation Operation, Hardware MONOZUKURI Division at Hitachi. “Hitachi is always aiming at high-performance, high-quality products, and in order to complete the design in the shortest cycle time possible while maintaining high quality, it was critical for us to solve the bottleneck of place-and-route for PCBs. By using Cadence GRE technology, we can solve the routing bottleneck as well as enhance the reliability of the design.”

The Cadence GRE technology is the next-generation interconnect planning and routing technology for PCB, and establishes a new PCB design paradigm. The GRE technology provides users with automation for various stages of interconnect planning and routing where no automation has been available. At the beginning of the process it allows users to plan the routing strategy at a high-level through Interconnect Flow Designer. Through the Interconnect Feasibility capability it checks and provides feedback on available space for each of the flows, allowing users to modify their routing strategy. In the middle of the planning process, it determines the overall routing feasibility, including the routing paths, net topologies and assigned electric constraints. In the final planning phase, the GRE technology performs feasibility routing against the pre-determined routing flow, and then automatically completes routing. This approach becomes very effective for memory interfaces such as DDR2, DDR3, and serial interfaces such as PCI Express and PCI Express Gen II with their stringent high-speed design constraints.

At Hitachi, automatic routing had not previously been available to route signals with high-speed constraints. The GRE technology dramatically improves the quality of PCB designs by enabling users to concurrently work on the placement and the exploration of the routing strategies and paths. With GRE, Hitachi was able to effectively manage PCB designs with various tradeoffs. Hitachi expects further reduction of design time as the GRE performance and features are updated and further enhanced.

“Cadence GRE technology is the next generation of PCB interconnect planning and routing technology. It offers automation for designs with high-speed interfaces such as DDR2, SATA, and PCI Express,” said AJ Incorvaia, vice president of research & development, Allegro - R&D Development at Cadence. “In order to design today’s PCBs with high-speed constraints while maintaining quality levels like those of Hitachi, it is imperative to make route strategy trade-offs at early stages of design as well as have a unified and global methodology for routing. By combining their high-level requirements PCB design with GRE technology, Hitachi is able to significantly shorten their overall PCB design cycle. This success will become a standard reference for a new design methodology for high-speed PCBs.”


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