31 March 2009
20% better transistor on-resistance in relation to active chip size.
A new series of 30 V surface-mount power transistors claim to achieve on-resistance of a maximum of 2 mΩ thereby increasing the energy efficiency of products such as computers, telecom and networking equipment.
STMicroelectronics used its STripFET™ VI DeepGATE™ process which has high equivalent cell density, to achieve the RDS(ON) in relation to active chip size. This is around 20% better than the previous generation and allows the use of small surface-mount power packages in switching regulators and DC-to-DC converters. The technology also benefits from low gate charge, allowing engineers to use high switching frequencies and specify smaller passive components such as inductors and capacitors.
The broad choice of industry-standard outlines, including SO-8, DPAK, 5x6 mm PowerFLAT™, 3.3 x 3.3 mm PowerFLAT™, PolarPAK®, through-hole IPAK and SOT23-6L, offer compatibility with existing pad/pin layouts maximising market opportunities for ST’s STripFET VI DeepGATE family.
The first devices introduced using this new process include the STL150N3LLH6, which offers the lowest RDS(ON)* per area in the 5 x6 mm PowerFLAT package. The STD150N3LLH6 has also been introduced, in the DPAK package, with an RDS(ON) of 2.4 mΩ.
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