Boosting Capacitance Figures While Keeping Down the Associated Footprint

Author : By Jürgen Geier, Technical Expert on Ceramic Capacitors at Rutronik

09 June 2024

Figure 1: Schematic diagram of a 2-chip element
Figure 1: Schematic diagram of a 2-chip element

The electronics market is demanding ever smaller system implementations and the integration of a greater depth of functions. This makes board real estate increasingly valuable. The following article looks at the importance of multi-layer ceramic capacitor (MLCC) components in efforts to save space.

MLCCs are compact, cost effective and reliable. These components have very low equivalent series resistance (ESR) values, which allows them to smooth high ripple currents. They are often used in place of and/or in parallel with electrolytic capacitors to improve system performance.

Figure 2: 2-chip element in through-hole design
Figure 2: 2-chip element in through-hole design

Due to modern miniaturisation demands, there is a growing need for capacitors with high capacitance values and improved temperature performance, but with smaller dimensions too. However, in the so-called HiCap range (=1µF) plus the mid-voltage range (covering 200V to over 450V) and high-voltage range (630V up to 5kV), they quickly reach their limits. This is because capacitors of size 1812 or larger (1825, 2220, 2225, 3640, etc.) are required here. Even with size 1210, which represents a certain performance optimum, multiple parallel connections and/or connections in series are required - that in turn call for comparatively large areas.

In addition to the capacitors, there are usually other, taller components on the PCB - so that, in principle, more height is available for the capacitors, but this is not used in single chip applications. To save space, several capacitors can be combined into 1 component. They are stacked and connected in parallel. Compared to a single element, this gives them a lower ESR and equivalent series inductance (ESL), as well as several times higher capacitance corresponding to the number of chips used. 

Figure 3: The leadframe gives the MLCC greater robustness against thermal/mechanical stresses
Figure 3: The leadframe gives the MLCC greater robustness against thermal/mechanical stresses

2-chip elements are most commonly offered in sizes 1210, 1812 and 2220, although in extreme cases even they are available with up to 10 chips and sizes up to approximately 30mm × 50mm. The individual chips are usually arranged horizontally with J-leadframes for surface mounting (see Figure 1).

Through-hole versions are also available (see Figure 2). However, they are used less frequently. This is partly because of the difficulty of automating the assembly process - which thereby leads to higher costs and longer production times. However, the structure of MLCCs with leadframes can also be used to increase the performance and robustness of single chip arrangements against thermal and mechanical loads (illustrated in Figure 3). Vertically stacked designs are also available for further optimisation, in terms of thermal stress and reduction of ESR/ESL (as shown in Figure 4).

Figure 4: MLCCs with multiple, vertically stacked chips offer low ESR and ESL plus a wide temperature range
Figure 4: MLCCs with multiple, vertically stacked chips offer low ESR and ESL plus a wide temperature range

As a further special feature, Kemet also offers such parts without leadframes. For this purpose, the supplier has developed its KONNEKT technology. This uses an innovative transient liquid phase sintering (TLPS) material to create a leadframe and lead-free multi-chip element. It guarantees further improvements in ESR and ESL, as well as increased volume efficiency. Capacitors using this material are also available with horizontally and vertically stacked chips.

In addition, special ceramics with positive DC bias are offered by TDK. Its CeraLink components are suitable for high-frequency and high-temperature applications in power electronics - especially where space is limited and nominal currents, capacitance densities and operating temperatures are heightened. Each CeraLink capacitor consists of a lead-lanthanum-zirconium-titanate (PLZT) ceramic in combination with copper inner electrodes. By balancing high current-carrying characteristics and capacitance, CeraLink technology allows the number of capacitors required to be reduced compared to MLCCs and the costs involved to be curbed. Unlike conventional ceramic capacitors, CeraLink capacitors have their maximum capacitance at the specified operating point (positive bias behaviour). This increases proportionally to the ripple voltage ratio, making them highly suited to fast-switching wide-bandgap (WBG) semiconductors - such as silicon-carbide (SiC) and gallium-nitride (GaN).


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