Debug/Trace Solution Offers CSWP Support

26 April 2024

Engineers developing systems using the Ambarella CV3 multi-core system-on-chips (SoCs), which are compliant with ASIL D functional safety requirements and can address autonomous driving implementations up to SAE Level 4, can now benefit from the debug/trace capabilities of Lauterbach's TRACE32 PowerView software.

This can be applied over the USB 3 interfacing of such chips via the Arm CoreSight Wire Protocol (CSWP) protocol (instead of having to use a conventional JTAG approach). The TRACE32 software means that developers can carry out debug and trace operations across all cores. Communication between the software and the CV3 SoCs is controlled by an Arm Cortex-M3 central processing unit (CPU).  

“As a technology leader in development tools for embedded systems, it was natural for us to support CSWP debugging from the very beginning.” states Norbert Weiss, Lauterbach’s Managing Director. “Ambarella's CV3 SoC family has all the chip-side prerequisites to enable customers to use our leading-edge debug and trace features without restrictions.”


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