Using 3D Modelling to Better Understand the Signal Integrity Influences of ESD Protection Devices

Author : Preethi Subbaraju, Development Engineer, Nexperia

28 March 2024

Figure 1: Typical configuration of a high-speed MDI - depending on specific requirements, ESD protection devices’ position can also be between the high-speed IC and DC block
Figure 1: Typical configuration of a high-speed MDI - depending on specific requirements, ESD protection devices’ position can also be between the high-speed IC and DC block

Major technological changes are currently underway that are looking to reshape the automobile industry. Among the most significant developments are requirements for enhanced connectivity, data transmission and infotainment options - for both drivers and passengers.

This demand has sparked a considerable growth in communication protocols, in-vehicle networks and automotive-related electrical applications. Specifically, the importance of high-speed data links (like USB, HDMI, etc.) and various video applications has risen significantly within this particular context.

With the increasing growth of electric systems in cars and the rapid increase in Ethernet data rates, it is imperative that in-vehicle networks exhibit improved signal integrity, electro-magnetic compatibility (EMC) and electro-static discharge (ESD) robustness. This article will explore the impact of a modern ESD protection on signal integrity using full-wave 3D modelling techniques. The findings will be examined in the frequency domain, specifically in relation to scattering parameters (S-parameters) and time domain reflectometry (TDR).

Figure 2: Stack-up of a typical 4-layer PCB - the dimensions were chosen to meet the 100Ohm figure for the microstrip line
Figure 2: Stack-up of a typical 4-layer PCB - the dimensions were chosen to meet the 100Ohm figure for the microstrip line

Figure 1 shows a typical configuration of a differential high-speed channel found in automotive designs. In this point-to-point (P2P) configuration, 2 system PCBs are connected with a shielded cable. Cabling will be in the form of a shielded twisted pair (STP) or shielded parallel pair (SPP). The part between the transmitter/receiver (Rx/Tx) and the cable is called a medium dependent interface (MDI) - containing the traces, DC block, ESD protection and connector for the STP or SPP. The following example will focus on the role of ESD in the MDI block.

Simulation set-up 
The investigation is done purely at a simulation level (CST MW Studio), therefore a 4 layer stack-up PCB with typical dimensions was chosen (see Figure 2). For the sake of simplicity and conserving simulation time, only 2 layers (the top-layer and GND) were used. The differential lines were routed on the top layer, while the GND was a solid layer without any gaps or openings. 

Figure 3: Details of the PCB employed
Figure 3: Details of the PCB employed

The PCB used had 2.5cm x 2.5cm dimensions (see Figure 3). The investigation solely examined the PCB region located between the connector and the PHY, with a particular emphasis on the traces and the consequences of incorporating the ESD protection device into them.

The simulation was performed using discrete, single-ended ports. No external fields were assumed, and the boundary conditions were set to OPEN (add space). All simulations were done by employing a frequency domain solver. For the prepreg, FR4 with er= 4.3 and tand = 0.025 at 10GHz would be used. For the conducting material, copper (with a conductivity of s=5.8e7 S/m) was chosen. The TDR was performed in a post-processing step using the S-parameters, and the rise time of the TDR signal was tr=100ps.

Figure 4: Model and simulation results of the differential transmission lines only
Figure 4: Model and simulation results of the differential transmission lines only

Simulation results in frequency and time domain
The 1st simulations focused on the traces only. Here, the microstrip lines would be modelled with the dimensions shown in the stack-up (see Figure 2). In order to establish an optimal electro-magnetic environment, grounding was implemented via a cage in close proximity to the microstrip lines. The results are shown in relation to frequency and time domain. The SDD21 differential S-parameters were calculated from the single-ended simulation in a post processing step. Figure 4 illustrates a typical transmission line behaviour, similar to a low-pass filter. The TDR results show a small mismatch in the microstrip line. This <1Ohm mismatch is within the typical manufacturing tolerances of the PCB.

In the 2nd step, series capacitors and the ESD protection device were added. It is worth noting the DC capacitors might show substantial impact on a real application, but within this simulation an ideal model of a capacitor would exhibit negligible effect, so this element was not explored further. As an ESD protection device, the PESD5V0H1BSF (with roughly 0.15pF) was utilised. The devices were modelled including the packaging (SOD962), as detailed in Figure 5.

Figure 5: Model and simulation results of ESD protection and DC capacitor components added to the differential traces
Figure 5: Model and simulation results of ESD protection and DC capacitor components added to the differential traces

Modelling including all package components, such as lead frame, housing etc. The dimensions and corresponding material parameters were taken into account. The S-parameters show a slight reduction in the bandwidth by adding the ESD protection device. In the TDR data, we see that the ESD protection device locally drops the impedance down to ~93Ohm, which is typical for ESD protection devices, due to their mainly capacitive behaviour. In most applications the tolerance window of the impedance along the PCB path is ±10% or even ±15%, which is consistent with the ESD protection device on the line.

Summary
The purpose of this article is to highlight the application of an ESD protection device in a state-of-the-art simulation environment, and the relevance to electronic engineering. Within the simulation environment, the ESD device can be implemented as a full 3D model. All package dimensions and material parameters can be included in this model. The purpose of the analysis is to demonstrate the performance of a portion of the MDI, which includes microstrip lines, DC capacitors and the ESD protection device. Modelling ESD protection devices as a full 3D model can be highly advantageous, particularly for high-speed interfaces that are sensitive to parasitic elements. Nexperia offers customers the opportunity to access multiple 3D models for specific ESD device packages, and further supports them by facilitating integration into their simulation environment.


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