Fully-Tested Multi-Core Environment for Development of RISC-V Based Chips

08 October 2023

Semidynamics has collaborated with Californian start-up SignatureIP on the creation of a fully-tested interoperable RISC-V, multi-core environment plus CHI interconnect.

It draws on the companies’ respective customisable 64-bit RISC-V processing IP and Coherent NoC IP elements. Consequently, this will be able to help speed-up and de-risk next generation chip design projects - so that demanding artificial intelligence (AI) workloads can be dealt with. SignatureIP’s Coherent NoC IP delivers strong performance alongside inherent scalability. It supports a transport layer for chiplet communication. Semidynamics’ multi-core architecture provides an easily configurable platform for designers to work with.  

According to Roger Espasa, CEO of Semidynamics; “Working closely together with other members of the RISC-V community is one of the driving forces of RISC-V’s rapidly growing success. There is a natural synergy between the two companies that has resulted in a solution that enables cutting edge, multi-cores chips to be created. SignatureIP’s C-NoC CHI interconnect solution makes it very straightforward to lay out the network on chip for multiple cores on a chip using our mature, proven technologies which minimises risks and accelerates time-to-market.”

“Combining our technologies now enables multi-core chip designs to be created on this fully coherent RISC-V/CHI platform and then prototyping on an FPGA to demonstrate the integrated performance. We have fully tested them together to ensure compatibility and minimisation of verification time,” Kishore Mishra, CTO of SignatureIP, concludes.


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