Industry's fastest RLDRAM I/II support

23 September 2008

FPGA-based support for RLDRAM I/II memory devices has been announced by Lattice Semiconductor.

The LatticeSC and LatticeSCM FPGA families (collectively referred to as the LatticeSC/M families) now support RLDRAM (Reduced Latency Dynamic Random Access Memory) I/II rates up to 800Mbytes/sec.

The high-speed RLDRAM I and RLDRAM II memory controller IP (intellectual property) is implemented in Lattice’s low power MACO (Masked Array for Cost Optimisation) structured ASIC technology.

The LatticeSC family is designed to provide the performance and connectivity for high-speed applications. Fabricated on Fujitsu’s 90nm CMOS process technology using 300mm wafers, LatticeSC FPGAs claim to accelerate chip-to-chip, chip-to-memory, high-speed serial, backplane and network data path connectivity.

Integrated into the LatticeSC devices are high-channel count SERDES blocks supporting 3.8Gbytes/sec data rates, PURESPEED parallel I/O providing 2Gbytes/sec speed, FPGA logic operating at 500MHz, and block RAM. Lattice’s MACO (Masked Array for Cost Optimisation) embedded structured ASIC blocks are also available on the LatticeSCM devices, delivering pre-engineered, standard-compliant IP functions such as high-speed memory controllers, SPI4.2, Ethernet MACs, and PCI Express control functions developed by Lattice to shorten end-system time to market.

Unlike the soft IP cores commonly used with FPGAs, the MACO IP functions are embedded into the devices, and apparently there is no distinct IP license fee associated with their use. These memory controllers claim to provide the industry’s fastest programmable memory interfaces supporting next generation RLDRAM I/II memory devices, as well as DDR I/II and QDR II/II+ memory devices. Lattice’s ispLEVER version 7.1 software design tool suite supports a complete HDL-based design and verification flow for LatticeSCM devices, as well as other Lattice leading-edge programmable device families.

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