Cadence Design IP portfolio in TSMC’s N5 process gains broad adoption among leading semiconductor & system companies

15 June 2022


20+ design wins awarded by leading semiconductor & system companies. Multiple first-pass silicon successes achieved with Cadence IP. IP silicon tested & characterised to ensure robust system interoperability. Early N3 & N4 customer engagements underway.

Electronics design expert, Cadence Design Systems has announced that a wide range of leading semiconductor and system customers have successfully adopted its comprehensive line-up of Cadence Design IP (intellectual property) in TSMC’s industry-leading 5nm process technology. Designed to the latest state-of-the-art interface standards, Cadence’s Design IP portfolio enables customers to develop the most advanced SoCs (system-on-chips) for the most demanding applications, including high-performance computing (HPC), artificial intelligence/machine learning (AI/ML), networking, storage and automotive. The IP portfolio from Cadence in TSMC’s N5 process includes 112/56/25/10 Gbps Ethernet PHY/MAC, PCIe 6.0/5.0/4.0/3.1 PHY/Controller, 40Gbps UltralinkTM D2D PHY, and complete PHY/Controller for GDDR6, DDR5/4 and LPDDR5/4x.

TSMC (Taiwan Semiconductor Manufacturing Company) is a Taiwanese multinational semiconductor contract manufacturing and design company. It is the world's largest contract manufacturer of semiconductor chips and the world's largest dedicated independent (pure-play) semiconductor foundry. It is also one of the first foundries to provide 5nm (5-nanometer) production capabilities, the most advanced semiconductor process technology available in the world.

Cadence’s design IP in TSMC’s N5 process delivers optimal power, performance and area (PPA) with rich feature sets to enable uncompromised differentiation, versatility and innovation for large-scale SoC designs. In addition, Cadence provides full subsystem deliveries with integrated PHY and controller IP to simplify integration, minimise risks and enable faster time to market.

TSMC worked closely with Cadence, our long-standing ecosystem partner, to enable leading-edge designs, which deliver significant power, performance and area improvements on our advanced technologies,” said Suk Lee, Vice President of the Design Infrastructure Management Division at TSMC. “The strong collaboration between Cadence’s Design IP and TSMC’s IP9000 teams promotes high-quality IP delivery to help our mutual customers achieve first-pass silicon success and faster time-to-market.”

Cadence has collaborated with TSMC for decades to provide high-quality silicon-proven IP on advanced process nodes to meet the most demanding requirements for HPC, AI/ML, networking, storage, and automotive applications,” said Rishi Chugh, Vice President of Design IP Product Management at Cadence. “The wide adoption of our Design IP in TSMC’s N5 process demonstrates the excellence and quality of Cadence’s Design IP, which is empowering customers to design highly differentiated product solutions.

The N5 Design IP portfolio is part of the broader Cadence IP portfolio that supports the Cadence Intelligent System Design strategy. Through the continued development of its comprehensive Design IP portfolio, Cadence is enabling customers to achieve SoC design excellence at advanced nodes. For more information, please visit:

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