Boost dynamic performance of broadband ADCs by some 10 dBFS instantly with spur reduction IP

30 May 2022

Benefit from an immediate design-free, dynamic performance gain with the new EV12AQ600/605-ADX4 device, featuring an integrated ADX4 license key, enabling enhanced dynamics when operating at up to a peak of 6.4 GS/s (single channel mode). The ADX4 post-processing algorithm, compatible with Xilinx Kintex Ultrascale FPGAs, delivers up to 10 dBFS of SFDR dynamic spurs reduction & close to 1 effective bit extra resolution in broadband applications.

Gain immediate, design-free access to a dynamic boost for the EV12AQ600/5
Hi-rel semiconductor specialist, Teledyne e2v has today announced the immediate availability of EV12AQ600/5 models featuring an integrated license key providing direct access to the novel ADX4 post-processing algorithm developed at SP Devices within the Teledyne group of companies. The ADX4 spur reduction IP dynamically attenuates spurious frequency components resulting from gain, offset and phase mismatches between the four ADC cores. Time-interleaving is a trusted and conceptually easy to comprehend architectural approach to boost ADC sampling rates. However, avoiding resulting spectral artifacts with calibration is especially challenging beyond 10-bit resolutions and in broadband applications.

Applied to the EV12AQ600/5, time-interleaving four cores quadruples the sample rate from 1.6 to 6.4 GS/s. The mismatch errors between the ADC cores reduce spurious free performance. ADX4 delivers a spurious free dynamic range (SFDR) boost of up to 10 dB. That boost is particularly noticeable in broadband applications, and as it requires no hardware design changes is available on demand. The ADX4 code module is simply programmed into the post-processing FPGA. A modification that can even be retrofitted in the field.

About ADC time-interleaving
High-resolution data converters are on an upward trajectory to acquire broader instantaneous bandwidths. A theoretically simple method to achieve higher sampling is by applying time-interleaving to existing cores. Here, multiple ADC cores are clocked on different phases of a common sample clock, allowing a higher density of samples of a signal to be acquired. This increased sample density offers a useful performance extension and works well with modest resolutions up to 8-bits, in which cross core matching is relatively easy to manage through standard mixed signal calibration and circuit layout schemes.

For 10-bit resolutions and above, especially operating into the gigahertz range, it is increasingly hard to ensure matching. As a result, sampling artifacts arise causing distortion and limiting measured dynamic performance. These high frequency mismatch errors are very challenging to mitigate in the analogue design domain. Consider that, for a 6.4 GS/s time-interleaved ADC to achieve 72 dB SNR (the theoretical 12-bit maximum) with a 3 GHz input signal, a cross core phase match of better than 12 fs is required.

Thankfully, over the last two decades, the cost of DSP (digital signal processing) resources has fallen significantly, now making it economically feasible to take an algorithmic approach to spur reduction. Teledyne SP Devices, with expertise in high resolution ultra-fast digitizers, is well versed in mitigation technologies with experience gathered from several decades work on a broad range of industry leading discrete converters.

Unlike a single or multi-point calibration, ADX4 digital error correction can deliver spur suppression even when the errors vary over frequency. Results are such that the unwanted aliasing spurs are suppressed into the noise floor.

Implementing ADX4
It could not be easier to gain ADX4 dynamic enhancements. Via the desired supply chain, customers need only transition their orders across to the -ADX4 options of their EV12AQ600/5 device. Moreover, they need to add the ADX4 module to their Xilinx FPGA (field-programmable gate array) code load. Job done.

ADX4 availability
The following component list indicates the current EV12AQ600/5 options shipping today with ADX4 license keys. Customers considering dual channel operation should contact Teledyne e2v directly to discuss the future availability of an ADX2 license key option.

Useful links
•    Teledyne e2v EV12AQ600/5 product page
•    Video link: Learn time-interleaved EV12AQ600 ADC mismatch error correction

About Teledyne SP Devices
Teledyne SP Devices designs and manufactures world-leading modular data acquisition and signal generation instruments. Their products utilise patented calibration logic, the latest data converters and state-of-the-art FPGA technology resulting in an unrivaled combination of high sampling rate and resolution. Products are available with a range of application-specific features and embedded, real-time signal processing. This helps customers overcome performance bottlenecks, shortens time-to-market and provides system-level advantages within a wide range of application areas. SP Devices' products are deployed across a wide variety of industries, including analytical instruments, remote sensing, scientific instrumentation, medical imaging and more. For more information, visit:

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