Case study: Faster wafer testing delivers organisation-wide benefits

Author : Bart De Wachter | Researcher | imec

01 May 2021

imec_NI_Case study_Faster wafer testing delivers organisation-wide benefits
imec_NI_Case study_Faster wafer testing delivers organisation-wide benefits

In this case study, Bart De Wachter, Researcher at nanoelectronics R&D & innovation hub, imec explains how its Semiconductor Technology & Systems Group went about solving the challenge of performing accurate electrical wafer-level tests in its semiconductor R&D fabrication (fab) process flow to detect issues at an early stage.

The full version of this article was originally featured in EPDT's 2021 PXI for T&M supplement, included in the May 2021 issue of EPDT magazine [read the digital issue]. And sign up to receive your own copy each month.

Using the PXI platform, with NI PXIe-4135 source measure units (SMUs), to build a highly parallel measurement system for use inside the wafer fab, imec was able to test wafers inside the fab, process the results and make much faster adjustments to the semiconductor process flow. This helped imec rework wafers at the right time to manage yield drops and streamline the R&D process flow, reducing costs and decreasing time-to-market of the newest chip-manufacturing techniques.

Leading independent European nanotechnology research centre, imec brings together companies from all around the semiconductor industry, including tool and material suppliers, integrated device manufacturers and foundries, fabless and fab-lite companies and application partners.   

Due to partnerships with leading tool and materials suppliers, imec can perform advanced semiconductor process development, offering partners the most advanced research infrastructure in a state-of-the-art 300mm wafer fab/clean room.

The research on advanced semiconductor technology processing R&D encompasses next-generation logic devices, advanced nanointerconnect research and heterogeneous 3D stacked integrated control (IC) system integration, ideal for forthcoming low-power mobile applications.

Challenges in the process flow
Wafer/chip processing is conducted by sequentially performing hundreds of dedicated process steps, beginning with a blank silicon wafer and culminating in a  fully functional chip. However, in an R&D environment with complex individual process steps, defects that occur anywhere in the process flow can mean a substantial yield reduction.

Testing chips/devices on wafers in the early stages of the process flow gives on-chip performance feedback and timely semiconductor process monitoring. As imec’s testing had no in-line electrical test contained in the fab, feedback was not available within the process flow. Therefore, wafers were taken from the fab and tested with existing parametric testers while incomplete. Wafers removed from the fab could not be replaced for more processing due to contamination issues, leading to substantial wafer losses and a significant delay in the project.

imec R&D test chip vehicles contain thousands of different sizes of transistors, resistors and capacitors, as well as small application circuitry. To fully characterise a semiconductor manufacturing process, all of this must be tested.

Using an in-fab semiconductor automated test equipment (ATE) setup capable of handling continuous testing could significantly shorten R&D timescales and reduce project cost. As none existed, imec began seeking a versatile, fast and accurate tester to support the many industry affiliation programmes. The setup needed to be comprehensive and cover all of the parametric and functional IC test needs. And it needed to be scalable for the future...

Read the full article in EPDT's May 2021 digital issue...

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