De-risk your use of RISC-V IP

Author : Sunil Sahoo | Software Product Manager | Aldec

01 February 2021

Aldec_De-risk your use of RISC-V IP

The RISC-V ISA has seen much adoption thanks to its customisable architecture & open-source business model. Naturally, the open-source ISA is also producing new open-source cores that target certain applications. But if you are planning to take advantage of these open-source RISC-V cores in a chip of your own, you must verify its customisation & implementation.

The full version of this article was originally featured in the February 2021 issue of EPDT magazine [read the digital issue]. Sign up to receive your own copy each month.

Here, Sunil Sahoo, Software Product Manager at electronic design automation (EDA) firm, Aldec discusses three different levels of verification that will give you confidence and reduce your overall development time.

In the same way that the term ‘ARM-based’ is used to describe a product feature – at the chip and system level – the same is fast becoming true for RISC-V. For example, one implementation of the core, by SiFive, is at the heart of the BBC Doctor Who HiFive Inventor IoT Coding Kit (Editor’s note: covered on EPDT 19th November 2020). Also, Microchip claimed to be first to market with a ‘RISC-V-based SoC FPGA development kit’; the FPGA in question being the OEM’s low-power PolarFire device (Editor’s note: covered on EPDT 16th September 2020).

Accordingly, RISC-V awareness stands to extend from the EDA community all the way through to end-product consumers. However, unlike the ARM architecture, the RISC-V instruction set architecture (ISA) is free and open-source. Also, while many readers may have only become aware of the ISA and cores in the last few years, RISC-V ISA development work started back in May 2010; as part of the Parallel Computing Laboratory (Par Lab) at UC Berkeley, in the USA.

RISC-V processor cores are based on the open standard ISA. In the words of RISC-V International (formerly the RISC-V Foundation, founded in 2015 and controlled by its members to drive early adoption of the core), the architecture is frozen, and software written for one RISC-V core will run on a similar one. Good news for software and systems engineers.

And good news for hardware engineers too: they have considerable flexibility over the implementation of the processor to target various applications, and can optimise it for performance, low power or security, for example. RISC-V International also points out that if you are implementing a soft RISC-V core in an FPGA, then the register transfer logic (RTL) code can be easily ported into an ASIC design flow.

To date, various commercial and open-source 32- and 64-bit RISC-V cores have been implemented in hundreds of CPUs and  SoC platforms. However, if you are taking advantage of the core’s availability as open-source fabless IP (for integration within a chip you are designing), you must test it for ISA compliance and functionally verify its implementation; not only the core, but also its interaction/integration with the rest of your design (including other IP, memory, comms, I/O, and so on).

Read the full article in EPDT's February 2021 issue...


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