Integrated transceivers enable small form factor phased-array radar platforms
01 December 2020
Phased-array radar systems utilise many transmit & receive channels to function. Historically, such platforms were built using separate transmit & receive integrated circuits (ICs). They used separate chips for digital-to-analogue converters (DACs) in the transmit (Tx) circuitry & analogue-to-digital converters (ADCs) in the receive (Rx) circuitry.
The full version of this article was originally featured in the December 2020 issue of EPDT magazine [read the digital issue]. Sign up to receive your own copy each month.
This separation led to large footprint, high cost, high power consumption systems to realise the channel count necessary to achieve the desired function, as well as typically requiring longer time-to-market due to manufacturing and calibration complexities. However, as Mike Jones, Principal Electrical Design Engineer & Peter Delos, RF & Microwave Technical Lead at data conversion, signal processing & power management semiconductor firm, Analog Devices tell us, a recent approach utilising integrated transceivers combines many functions once considered disparate into single ICs. Using these ICs enables smaller form factor, lower power consumption and cost, high channel-count phased-array radar platforms with faster time-to-market.
Integrated transceivers, such as the one shown in Figure 1, combine multiple functions onto a single IC. For example, the new transceiver integrates DACs, ADCs, local oscillator (LO) synthesizers, microprocessors, mixers and more into a single 12 mm × 12 mm monolithic product. In addition, this product combines two receive channels and two transmit channels, as well as digital signal processing (DSP) components to achieve the desired instantaneous bandwidths required for the system. An application program interface (API) is also provided to operate the transceiver on a customer platform. Gain and attenuation control can be achieved by utilising the on-chip front-end networks. Built-in initialisation and tracking calibration routines are offered to provide the performance required for many communications and military applications.
These integrated transceivers are capable of creating all the clock signals needed for the transmitters and receivers by injecting a single reference clock signal known as REF_CLK. On-chip phase-locked loops (PLLs) then synthesize all required clocks for the DAC/ADC sampling, LO generation and microprocessor clock. If the internal LO phase noise is not sufficient for a customer’s application, the user can alternatively inject their own low phase noise external LO.
Read the full article in EPDT's December 2020 issue...
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