Signal integrity tests & debugging on digital interfaces
01 August 2020
R&S RTP164 oscilloscope with R&S RT-ZM 160 probe_580x280
High speed interfaces, such as USB 3.1 Gen1/2, PCI Express Gen2/3 or DDR3/4, require capable test & measurement equipment for startup and debugging during development.
This tutorial was originally featured in the August 2020 issue of EPDT magazine [read the digital issue]. Sign up to receive your own copy each month.
And as Guido Schulze, Product Manager – Oscilloscopes at electronics & wireless T&M experts, Rohde & Schwarz tells us here, ensuring sufficient bandwidth to capture the high-speed signals is only part of the story. Features to assist capturing and assessing eye diagrams, and analysing differential and common-mode signals, can help get results faster and make life easier.
To develop USB and PCI Express interfaces for today’s electronic devices, as well as other high-data-rate interfaces, such as display and camera interfaces, engineers need laboratory test & measurement equipment that can keep pace. When designing high-speed modules and interfaces, it is necessary to ensure that signal paths through features such as connectors, PCB tracks and vias are properly dimensioned to avoid impairing the targeted maximum data rate and minimum error-free transmission time (bit error rate).
Testing serial interfaces with data rates up to 10 Gbit/s
Real-time oscilloscopes are ideal for the required signal-integrity measurements. However, their bandwidth must be at least three times the fundamental frequency of the digital signal. For example, measurements on a third generation PCI Express interface with a maximum data rate of 8 Gbit/s require a 12 GHz oscilloscope. 15 GHz bandwidth is needed for USB 3.1 Gen2 with 10 Gbit/s signals. For protocol data decoding, the measurement bandwidth should match the data rate of the interface being tested.
Figure 1. Data eye of a 5 Gbit/s USB signal using CDR based triggering
Eye diagram tests
Eye diagram tests are one of the main tools for assessing transmission quality. Error-free data transmission can only be confirmed by an open eye diagram. However, the jitter (deviation of signal edges on the time axis) and noise (deviations in the signal level) must be observed over an extended period to obtain statistically adequate measurement reliability. This is very time consuming when using eye-diagram functions that can only perform calculations for individual waveforms in post-processing.
Hardware-accelerated clock data recovery (CDR) is a feature of the latest 13GHz and 16GHz R&S®RTP oscilloscopes that can help overcome this limitation. CDR extracts the embedded clock signal from the serial interface signal, and can be selected for every input channel of the oscilloscope. The extracted clock signal acts as a time reference for triggering and displaying the waveform and eye diagram. Using CDR as the trigger reference, the oscilloscope “sees” the data exactly the same way as the serial interface receiver, which also uses CDR. Figure 1 shows an example eye diagram captured using the R&S RTP-K141, which has a serial pattern trigger option with hardware CDR that supports data rates up to 16 Gbit/s.
If the user selects an “X” as the trigger condition with CDR-based triggering, the symmetrical eye diagram of the interface signal is displayed on the screen by superimposing arbitrary bits (Figure 2). With an acquisition rate of up to 750,000 waveforms per second, the eye diagram is quickly formed from superimposed bit sequences. The resulting image allows infrequent errors to be quickly detected.
Figure 2. Settings for the serial pattern trigger with hardware CDR for fast & continuous eye diagram tests
Analysing jitter, noise & intermittent errors
Further analysis of the eye diagram using internal hardware-based histogram and masking tools can quantify jitter and noise in addition to helping track down causes of intermittent errors.
Figure 3 shows the jitter and noise behavior of a PCI Express signal (8 Gbit/s). This is obtained by taking vertical and horizontal histograms of the eye diagram. The jitter histogram shows a bimodal characteristic, which arises from deterministic jitter. The standard deviation, which is dominated by random jitter, can also be determined by automatic measurements on the histogram. This data provides important insights regarding the signal integrity of the interface under test.
Intermittent errors in a serial interface can be detected by observing a continuous eye diagram based on the embedded clock signal. Masks in the eye diagram are defined for this purpose. Violation of the mask area by a signal waveform indicates an error. If the oscilloscope is configured to stop on violation, it terminates acquisition for further analysis. The history function can be used to access previous waveforms in the acquisition memory to deduce the root cause of the error, which may involve other signals, such as the supply voltage.
Differential signal analysis
Figure 3. Using vertical & horizontal histograms to investigate the jitter & noise behaviour of a 3rd generation PCI Express signal (8 Gbit/s)
High-speed serial signals are usually carried over differential lines. Depending on the contact options, differential signals can be measured either with a differential probe, or by connecting two separate lines to two input channels of the oscilloscope.
Differential signal components can be calculated from measurements with two channels. To do this, the oscilloscope places a math module immediately after the A/D converter and equalisation filter in the signal-acquisition path. The user can select any two oscilloscope channels as the input signals. The differential and common-mode signals are both available for further processing and analysis. The digital trigger system uses the data from the A/D converter to let users trigger on the corrected differential signal component, and hence quickly track down errors in the common-mode signal.
Protocol analysis with targeted triggering
Along with signal integrity testing for circuit commissioning, engineers often need to analyse the data of high-speed serial interfaces at the protocol level. One example is if state-machine errors occur when the data link is booted. This can be done by triggering on the data sequences of specific protocols using the serial pattern triggering option provided by RTP oscilloscopes. Among the decoding schemes supported are 8-bit/10-bit decoding, as used in USB 3.1 Gen1 and PCI Express Gen2 up to 5 Gbit/s, and 128-bit/132-bit decoding, used in USB 3.1 Gen2 at 10 Gbit/s.
Startup and debugging of electronic circuits with fast digital interfaces, such as USB or PCI Express with data rates up to 10 Gbit/s, demands an oscilloscope with features created specifically for effective signal integrity tests. To choose a suitable instrument, look for a high acquisition rate, hardware CDR up to 16Gbit/s for eye-diagram analysis, tools for handling serial differential signals and serial pattern triggering support for protocols up to USB 3.1 Gen 1/Gen2.
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