Dual Baseband design for global talking
25 July 2008
When contemplating world travel, mobile handsets make MP3 players, navigation devices, and cameras redundant; but the phone is redundant when it does not work in the destination country
Countries such as Japan and Korea support a different standard (CDMA and FOMA) from most of Europe,
which only supports GSM. Many other countries support both standards (GSM and CDMA), and it largely depends on the carrier. Therefore, a single handset cannot be used worldwide. As a result, many travellers carry two phones or purchase a new SIM card at the airport whenever they travel and then inform friends and colleagues of their new number.
With telecommunication technology continually improving, data transferred by air is no longer in the Kbyte/sec range as in 2.5/2.75G phones. Modern 3.5G, HSPAcapable phones require data transfer in the kByte/sec range. Future mobile communication standards that are currently being trialed, such as WiMax, WiBro, LTE and UMB, will further extend data transfer rates. To match the increased speed provided by these new standards, handset processors have been improved and cellular networks have been upgraded to handle the increase in data throughput.
Nevertheless, with the increase in processing power of baseband processors and the increased data capabilities of mobile networks, there remains an antiquated inter-processor communication architecture
within the handset that is limiting its capability to perform at its optimum. Indeed, it could be argued that this portion of the telecommunication ecosystem has not been developed as far as other technology in the mobile handset.
Currently, handsets contain a baseband and an application processor, each capable of many MIPS (million instructions per second) and data rates achieving 10Mbit/sec or more for HSPA-capable phones. With the
focus on processor capabilities and wireless data rates, the communication between processors has been a high-profile bottleneck. This is a problem faced by numerous handset designers that have the latest
processors and chipsets, but are unable to increase the performance of their devices. Current handset
architectures use various means of interprocessor communication, and the popular direct interfaces currently in use include SPI, I2C, UART, and USB.
Although SPI is capable of data rates in excess of 20Mbit/sec, a lack of uniform specification means that it is dependent on the processor used. Typically, the SPI implemented by baseband processors offers 16Mbit/sec throughput. The difficulty for the handset designer is to pair two baseband processors from two different manufacturers that will have used their own proprietary implementation of SPI. Achieving optimum SPI speeds in these circumstances is an arduous task.
Initially, I2C appears to be more appealing. Although the latest high-speed version of the I2C provides data rates up to 3.4Mbit/sec, most devices available are only capable of supporting data rates between
400Kbyte/sec and 1Mbit/sec. At these speeds, I2C is considered too slow for today’s broadband wireless networks.
The third type of interconnect used in handsets is UART. The typical data rate is around 1.5Mbit/sec, although high-speed UART is capable of up to 5Mbit/sec. However, such data rates are insufficient for
high-bandwidth interprocessor communication.
One of the more popular interconnect technologies is USB. Most processors are equipped with FS-USB (full speed USB) device capability, and although a maximum data rate of 12Mbit/sec is possible, throughput in
real systems is typically closer to 6Mbit/sec due to the high packet overhead in the USB protocol. Furthermore, most baseband processors are not equipped with the host capability that USB requires, so an additional USB host has to be included in the design. As the USB host is constantly active, (even when no data is transmitted), power consumption is increased. Also, the number of USB ports available on a baseband processor is usually limited, since a port is always required for connecting the handset to a PC.
When handsets were required to send text messages and transfer data on slower networks, the interconnection methods mentioned might have been sufficient. With HSPA-capable handsets specified for data rates of 14.4Mbit/sec or more, none of these interfaces are adequate. Designers therefore need to address today’s need for increased data throughput in handsets.
The multi-port interconnect is entirely different from interface standards and is gaining currency amongst handset designers. It consists of high-speed memories with access times as short as 40nsecs and a dual-port interconnect available from Cypress Semiconductor can support up to a 400Mbit/sec data rate. This provides support for HSPA-capable handset requirements as well as laying foundations for future higher-bandwidth technologies. As handsets become more sophisticated, it is inevitable that more data will need to be transferred between processors. By using a multi-port interconnect, handset designers no longer have to overcome an inter-processor communication bottleneck.
As well as high speed, low power consumption is a key requirement for mobile handsets. If both basebands are required to be active during inter-processor communication (as in the case of SPI, UART,
I2C or USB), battery life will be decreased. However, a multi-port solution enables passive communication between the processors. As a processor can write to the multi-port interconnect when it needs to and then enter sleep mode, the other baseband processor can access data at its own convenience. With the multi-port interconnect acting as a buffer, the receiving processor can be in sleep mode until it receives the interrupt from the multiport interconnect before going active.
It seems that the traditional interconnects can no longer support the necessary data rates. Some handset designers have started to realise this impending problem and have therefore switched to using lowpower
multi-port interconnects. These provide the high bandwidth and low power consumption needed in modern handset design, as well as provide flexibility for designers to produce improved handsets at lower cost with a faster time to market.
MING HOONG CHONG is associate product manager, Cypress Semiconductor
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