Why modular instrumentation is critical for system-level test

Author : Jeremy Twaits, Senior Field Marketing Engineer at National Instruments

07 May 2018

System-in-package (SiP) technologies are making a significant impact on the electronics supply chain, as the semiconductor industry strives to meet the perpetual demand for higher performance, smaller size and lower cost.

SiPs contain two or more dissimilar dies, typically combined with other components (such as passives, filters, MEMS, sensors and antennas).

The guaranteed system-level performance and plug-and-play nature of SiPs lowers the design burden for companies looking to differentiate based on product style rather than electronic design. As this article explains, with the expectations for strong SiP growth, the race is on to meet challenges ranging from assembly and packaging technologies to test and validation.

With the inclusion of RF components, for example, shielding poses a significant challenge for the assembly design process. On the test side, dies integrated into SiPs are tested and generally meet known-good-die criteria; however, when multiple dies are combined – often with added active and/or passive components – the performance of the SiP as a system must be verified and warranted.

E. Jan Vardaman, president and founder of TechSearch International, a leading consulting company in the field of advanced semiconductor technology, commented: “The testing of SiPs can be challenging, and design for test is important. SiPs often include multiple functions and features that may not lend themselves well to traditional test approaches.”

Implications for test

In recent years, system-level test (SLT) use has grown more important in guaranteeing the overall performance of SiPs in their end-application environment. An SLT environment emulates the end-application environment in electrical, physical and software forms – and ideally covers 100% of the environmental scenarios. Today, finding a commercial off-the-shelf (COTS) test solution that meets these requirements can be difficult, particularly due to the following challenges: device handling; high-level communication; application load boards; and increased analogue and RF.

Increased analogue and RF

SiPs often incorporate multiple sensors and power management blocks, along with radios for one or more RF standards – including Wi-Fi, Bluetooth, GPS, NFC and 2G/3G/4G cellular communications. Consequently, the tester needs to provide robust analogue and RF I/O, which may resemble that of high-performance ATE.

PXI is ideal for implementing systems that require such a mixture of measurements. The ability to pick and choose between hundreds of modules from dozens of manufacturers, and to integrate them into a single chassis, allows the engineer to customise the system for their device under test (DUT). With PXI systems spanning from high-precision DC to mmWave frequency RF, the majority of common measurement requirements are covered. Another key advantage is that as new generations of SiP are released, PXI instrumentation – given its flexibility – will continue to accommodate the necessary change.

Consider, for example, future devices that will support the 5G New Radio air interface. SiPs will need to support wider bandwidths, higher frequencies and new waveforms, and the software-defined nature of PXI will be an important factor in solving many of these challenges. For instance, using software that is compliant to the latest 3GPP specification will be critical to supporting new, carrier-aggregated waveforms.

Integrated Device Technology (IDT) deployed the PXI-based NI Semiconductor Test System (STS), in order to keep pace with increasing test performance requirements. Glen E. Peer of IDT commented: “Traditional ATE systems require major costly retooling efforts on the test floor as generations of test systems become obsolete or unable to meet new test requirements – but the nature of the pen PXI architecture of the STS helps us retain our original investment and build upon it, rather than throw it away. It provides the flexibility we need to reconfigure and grow our test platforms in parallel with our growing performance needs.”

High-level communication

On the electrical and software side, SLT usually contains elements of both IC test and end-device test. For example, communicating with an SiP may use device-specific protocols (like communicating with an end device such as a smartwatch), instead of using digital patterns that are common with automated test equipment to test at the IC level.

The PXI platform offers numerous options for communicating via custom protocols. Most commonly, this is performed via high-speed digital or serial instruments, which often utilise a LabVIEW-programmable FPGA for application-specific customisation and reuse.

Device handling and application load boards

The potentially long test times required for SLT pose mechanical handling challenges, which typically include both the ability to load and unload asynchronously, and the capacity to handle many sites (often several hundred) – ultimately providing high throughput. SLT load boards may be specially designed to emulate the end-application environment. For example, the load board of an SiP intended for a mobile phone may resemble the reference design of the mobile phone.

National Instruments has addressed these challenges by deploying PXI instrumentation into its NI Semiconductor Test System (STS). Its ‘tester-in-a-head’ design houses the key components of a production tester, including system controllers, instrumentation, device-under-test (DUT) interfacing and device handler/prober docking mechanics.

IDT’s Peer commented, “Unlike our previous hybrid approach, with STS, we could consolidate the test head, which reduced the number of potential failure points within manufacturing, downtime for maintenance, and repair and floor space requirements. We also increased our ability to test a wide range of devices with the same configuration because the system has interchangeable interface boards, and we can use the same tester configuration for different device types.

The multisite system allows for higher test throughput because it is a true parallel test system with high-accuracy performance parameters for hardware optimisation. Lastly, this solution was lower in cost compared to alternative integrated solutions, because we needed to build only one set of instrumentation and we had fewer individual systems to maintain.”

Early success with the modular approach

Whether or not you work in the semiconductor industry, systems-in-a-package are likely to have an impact upon you. For most of us, the benefit will be seen in the size reduction of electronics within mobile devices and wearables, for example.

For engineers and engineering managers working within the semiconductor industry, the impact will be felt in the design and test challenges that must be overcome. Understanding the roadmap of SiP offerings from your suppliers is important because it will likely have a significant impact on your design options.

Many of today’s successful system-level test implementations for SiPs centre around high-performance, flexible test platforms – and PXI is ideally placed to meet this need. As an open, industry-standard platform that readily accommodates device-specific requirements, PXI is primed to ensure that the technology investments you make today will evolve with your requirements in the future.

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