How to select NAND flash
08 February 2008
Figure 1: NAND solution options
Portable media players and GPS are examples of denser mass storage requirments to satisfy more multimedia.
NAND flash has become the prevalent choice for mass storage in consumer applications due to its lower cost per bit and higher densities advantages over NOR flash, and its smaller size, power and robustness advantages over hard disk drives. As demands are so high, storage prices are decreasing dramatically and other devices such as POS (point of sale) terminals, printers can take advantage and use higher density storage at these lower costs. However, as the demand for density surges in these embedded applications, designers are faced with the challenge of selecting from a variety of NAND flash types, densities, vendors, roadmaps as well as implementations.
The first and most important selection criterion for a NAND flash solution is the implementation of the NAND controller. All NAND flash devices require maintenance overhead located in software and hardware of an external controller to ensure reliable data, maximise the lifespan of the NAND flash device and to enhance performance. The three main functions of the NAND controller are called bad block management, wear-levelling and error correction coding (ECC). NAND flash stores memory in clusters called blocks. Most NAND flash devices will inherently be built with some bad blocks that will be found upon testing conducted during manufacturing, and these blocks will be labelled as bad in the device specification by the vendor. In addition, good blocks may degrade over the life cycle of the NAND and should be tracked in software. Tracking of bad blocks is called bad block management. The consistent read and write to a particular block may cause the block to ‘wear out’ in NAND and become a bad block. In order to ensure maximum life cycle of the NAND and limit the amount of blocks that wear out, all blocks should be read and written to evenly in a process that is called wear-levelling. Finally, bit errors may occur due to inactivity or operation of a particular cell and ECC must be implemented in either software or hardware to detect and correct these errors. ECC is typically defined as the number of bits the code can correct per 528byte sector. In a system, this NAND controller can be combined with the NAND in the three different configurations (see figure 1).
SLC or MLC
A designer must also choose between two types of NAND flash devices, SLC (single-level cell) NAND and MLC (multi-level cell) NAND, each of which offers its own benefits. SLC NAND provides longer life cycle and reliability of each block, therefore requiring less ECC and offering superior performance. MLC NAND has lesser performance, is more difficult to implement since it requires higher levels of bad block management, wear-levelling and ECC, but is roughly one third of the price of SLC NAND per bit. Because of the increasing differential of cost between SLC and MLC NAND most applications are moving to MLC NAND, especially in higher density type applications, in order to substantially decrease bill of material costs.
Selection is based on multiple factors including mMicroprocessor NAND controller support, the type of NAND being used and the density of NAND required on the platform. In platforms where designers are using a microprocessor that has a full NAND interface and controller, option 1 is typically the preferred choice. Most contemporary microprocessors, if they have any support for NAND at all, typically only support SLC NAND in lower densities. The process technology limits the amount of storage on a die of SLC or MLC NAND, as currently this density is at about IGbyte of storage per die. Therefore, in order to support higher densities of NAND, a controller must be able to support multiple NANDs, usually done by an interleaving process and multiple chip-enables.The addition of multiple chip-enables to support multiple NANDs can drive the pin count of a microprocessor higher, which makes inclusion of this type of NAND controller less prevalent.
As process technologies nodes of MLC NAND move lower, the levels of error correction required to support this type of NAND become higher. Currently, levels of error correction needed for MLC NAND are at 4bit, but are quickly moving to 8bit and 12bit. The higher amounts of ECC require hardware in the NAND controller. Microprocessor evolution is moving at a slower pace than the rapidly evolving MLC NAND.
Memory card options
The ‘controlled NAND’ type solution shown in option 2 is used in several different embedded and removable types of storage. All portable SD/MMC cards use this type of implementation, and there are several choices for embedded controlled NANDs. Advantages are that the microprocessor only needs to support an SD/MMC type interface to add system support for either SLC or MLC NAND. The controller is stacked with the NAND and handles all bad block management, wear-levelling and ECC for the NAND. Controlled NAND solutions are seen currently at roughly 4Gbyte densities in embedded solutions and at 8Gbyte in removable cards. The disadvantage with this solution is that each NAND vendor supports different interfaces on their variety of controlled NAND (one may use SD, one may use MMC, another may have a proprietary interface), and switching from one NAND vendor to another requires a complete software overhaul.
The solution presented in option 3 gives the designer the most flexibility in choosing the type of NAND as well as in choosing from different vendors. Almost all NAND controllers support different types, vendors and densities of NANDs, and because the NAND controller will always use the same interface to the processor, the designer is free to choose different types and vendors of NAND without having to change any software. The block diagram displays the Cypress West Bridge Astoria device, a multimedia mass storage controller with full SLC and MLC NAND management.
Astoria provides multiple processor interfaces such as SRAM, ADMUX, SPI, and NAND and can support up to16 SLC or MLC NAND devices from any NAND vendor with 4bit ECC using Cypress’ proprietary N-Xpress technology. This gives designers choices on the types of density, as well as the ability to change NAND vendors on the fly, with little to no software changes on the microprocessor. Using an external NAND controller can also provide other benefits. For instance, the Astoria has a high-speed USB interface that bypasses the main processor and provides a direct path to mass storage from a PC in applications such as portable media players, and handsets giving optimal sideloading performance. Astoria also supports SD, MMC and SDIO, which means a designer can connect an SDIO type device such as WiFi, or Bluetooth if the system’s microprocessor is limited on SDIO interfaces.
If indeed the system’s microprocessor has a built in SLC or MLC NAND controller, this solution would be most beneficial as it would not require any external device or logic. A controlled NAND solution is often beneficial as a total NAND solution packaged and made by the NAND vendor that also requires no external logic or chip. An external NAND controller provides the most flexibility for all NAND types and can add additional benefits such as performance and interfaces, but requires an external chip.
STEPHAN HARRIS is product manager, Cypress Semiconductor
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