Multitasking multimedia in modern handsets

01 March 2007

As consumer expectations drive the handset from purely a communication device to a multimedia hub, the need for it to support different types of media concurrently is vital

Today, the handset not only needs to maintain its original purpose as a method of communication, but it also needs to be a high-end music player, a digital camera, and a modem for the PC. In order to support all of these requirements, it has to have efficient and optimal transfers of data.

One particular bottleneck in existing architectures of handsets resides in the high-density transfers of music, picture and video files from the PC to the handset. Currently, handsets use full-speed USB for these transfers, with the main processor, called the baseband processor, facilitating these data intensive operations. Because the baseband needs to be involved in the high data transfers, combined with the use of the slower full-speed USB instead of high-speed USB, the net result of existing designs is a handset that cannot be used for communication and has slow PC to handset transfers. Figure 1 is a block diagram of existing handsets.

Demonstrations done by various consumer reports show that this type of architecture results in download times of roughly an hour for 100 mp3 files. This type of performance is unacceptable for the consumer that expects high-end portable media player quality download speeds.

To resolve this issue, the first identified improvement is to use a high-speed USB controller. The full-speed USB technology has a raw throughput of 12Mbit/sec, whereas for high-speed USB it is 480Mbit/sec, an improvement of 40 times.

USB devices
In any system, a fullspeed or high-speed USB device contains several standard components. It must contain buffers that store USB data, typically called endpoint buffers, a serial interface engine (SIE), a USB transceiver (PHY), configuration/status/ control registers and program memory to store the USB software stack. The endpoint buffers store all of the USB data and are often structured in a first in, first out (FIFO) architecture. The SIE’s function is to send and receive data to and from the endpoint buffers. The SIE detects and creates the standard USB packet signals as well as encoding and decoding USB data onto the parallel bus that communicates with the PHY. The PHY is an analogue switch that is the hardware interface between the parallel bus of the SIE and the serialised D+ and Dlines of the USB connector.

In handsets, the analogue USB PHY will never be integrated into the digital baseband processor due to certain technology constraints. Most baseband processors have integrated the digital full-speed USB components, however, few baseband processors have support for high-speed USB. For the baseband processors that have support for high-speed USB there are two types of high-speed USB PHYs from which to choose. The choice of the PHY is based upon the high-speed USB interface on the baseband processor. The first interface is the universal serial bus transceiver macrocell interface (UTMI), which has a minimum pin count of 22 pins and maximum of up to 46 pins. The second interface is the UTMI low pin interface (ULPI) that reduces the pin count between the digital baseband and analogue PHY to six to eight pins and also reduces the size of the PHY by lowering its pin count. Figure 2 shows the block diagram of the architecture with the Cypress MoBL-USB TX2, a high-speed USB PHY.

For baseband processors without support for high-speed USB, this functionality can be added to the handset using a full USB controller solution that includes the digital and analogue USB blocks integrated into one chip. The Cypress MoBL-USB FX2LP18 is shown as an example of this type of solution in figure 3.

The solutions solve the issue of slow download speeds from the PC by adding support for high-speed USB to the handset. Both architectures reduce the download of 100 songs from an hour to less than five minutes.

These architectures still require the involvement and bandwidth of the baseband processor in the highly data intensive transfers from the PC to handset storage. This slows down the transfer of data from the PC, as the baseband processor will need to handle communications, the operating system and other tasks. This problem can be resolved by using a high-speed USB/mass storage bridge type device, such as Cypress’s West Bridge Antioch peripheral controller.

Immediately it can be seen that the baseband processor is now offloaded from the data intensive transfers, freeing up critical handset resources and reducing download time from the PC. The two-step process from the PC to mass storage shown in figures 2 and 3 is now reduced to a single step. The download time of 100 mp3s now decreases from five minutes to 30sec. As the handset consumer begins to drive the need for higher density storage, there is a likelihood of transfers up to 500 mp3s, and this additional reduction in transfer time is essential.

The bridge solution
The simultaneous usage model enabled by the bridge solution is also necessary for multitasking multimedia. As cellular communication technologies evolve from 2G and 2.5G technologies such as CDMA, GSM, GPRS and EDGE to 3G and 3.5G technologies such as CDMA2000 EV-DO, WCDMA, HSDPA and HSUPA, the data rates of these technologies are approaching 14Mbit/sec. The handset can suddenly be connected to the PC and used as an Internet connection. Also, as handset cameras improve to 3.1 megapixel and beyond, the amount of picture data transfers from the handset to PC increases. Faster PC synchronisation is becoming a requirement as e-mails and file sizes become larger. All of these usage
models can be enabled simultaneously by the Cypress West Bridge Antioch solution, which features 16 USB endpoints. The amount of endpoint buffers in the bridge solution dictates the level of multitasking that can be enabled in the handset.

The design and life cycles of the baseband processors are longer than the other companion chips in the handset. Another value of having a bridge type solution is that since its design cycles are shorter, it can add support for mass storage interfaces that may not be included on the baseband. For example, the West Bridge Antioch peripheral controller includes support for the latest handset storage devices such as secure digital (SD), multimedia card (MMC), hard disk drive (HDD) and NAND flash. Not only does this functionality increase the ability to connect to the latest storage devices, but it also improves performance.

As with all handset solutions, the ‘Four P’ criteria (package, price, performance and power) are important considerations. The Cypress solutions in figures 2, 3 and 4 all have their individual niches in the handset market. However, as consumer demands push the handset toward a media hub, the West Bridge Antioch bridge type solution will become more of a necessity, adding overall value to the handset, and enabling the level of multitasking that the consumer will require.

STEPHEN HARRIS is product marketing engineer, Cypress Semiconductor


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