Verification addresses low-power logic

01 April 2007

As more portable devices need a longer battery life, the need to make power savings is moving to integrated, high-performance, 90nm and below silicon. The lower processes can create heat management issues, which can be resolved by optimising power throughout the chip, writes TOM BRESLIN.

Advanced low-power design tools, such as power shut-off, multi-supply voltages and stateretention power gating are increasingly used to meet power and packaging considerations.

Now, instead of using different tools to specify low-power functionality, for example manually entering power data multiple times in a single design, Cadence has announced an integrated, standardised flow for logic design, verification and implementation of low-power chips. This process is labour-intensive and prone to error and makes predictability and verification difficult.

The Cadence Low-Power Solution ( establishes a single representation of the power intent. Verification and implementation is integrated with Common Power Format (CPF) which is a standardised format for specifying power saving techniques, early in the design process. The CPF lexicon
can be recognized from design, through verification and implementation. The power intent is established in the CPF, making IP reuse and RTL portability easier. By preserving low-power design intent throughout the design, a degree of manual work can be eliminated and contribute to reducing power-related chip failure, with power predictability. improve design predictability. The representation is used across the design
methodology, flow management, simulation, logic synthesis, equivalence checking, placement, routing and IR drop analysis.

The solution claims to be the first to automatically instantiate low-power techniques at the register-transfer level, able to operate throughout the verification, front-end implementation and physical implementation,
using a common format. According to Cadence, the approach has already been used by NXP Semiconductors and Analog Devices. Logic designers, verification engineers and implementation engineers can work from a common view, including power intent to

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