Cadence lays out holistic approach
01 August 2006
Fister: holistic advocate
In today’s design world, there is an increasing integration of RF and mixed signal design with hardware and software integration. These bring technology risks; experimenting with technology under time and budget constraints and make demands on performance and power consumption objectives. Mike Fister, president and CEO Cadence Design Systems identified a holistic approach to the development cycle, at CDNLive! (Cadence Designer Network) conference, last month.
This end-to-end and collaborative idea puts verification at the top of the agenda. It also dovetails with the company’s offering of development kits that are designed to help customers enter new design domains and
improve methodologies so that the resulting designs hit budget and schedule.
The company has introduced the Precision Router, a space-based, chip and block routing for advanced mixed signal, analogue and custom digital designs. As processes shrink designs are complicated by the wavelength of light which is three times smaller with each reduction. The Precision Router helps the design team to understand the lithography issues with 65nm geometries and beyond. A hierarchical approach breaks down all the levels of lithography, for example the CMP (chemical mechanical polishing) level. It introduces corridor routing and converges that with the complex interconnect rules of 65 and 45nm processes for early prediction. It uses three dimensional, space-based modelling to analyse shapes and the intervening spaces which is claimed to provide greater accuracy, precision and flexibility over shape-based approached to crating, checking and manipulating interconnects. It also minimises, according to the company, the steps to design and manufacturing convergence. The Router operates seamlessly with the Virtuoso design platform to provide a hierarchical and constraint-driven design closure environment, with incremental interactive and automatic routing.
Fister used CDNLive! to explain how the EDA industry has evolved. A platform-based approach, with processor core and memory integrated brings verification IP into the mainstream. Similarly, hardware and software integration demand more simulation and hard implementation. Abstraction levels are becoming more complicated with the growing integration. Now, designers need to consider the effects on neighbouring component parts. As a result, manufacturing, tools and methodology, verification, eco-systems, power management and technology risk and product scheduling all join together in the design considerations.
It is a given that increasing the level of verification reduces the risk associated with a new product design. Another announcement speeds verification of ARM-specific technology, the Functional Verification Kit for ARM processors. The kit covers architectural verification to system validation for both hardware and software with Cadence’s Incisive Plant-to-Closure methodology. It is targeted at verification in wireless and digital personal entertainment markets, using ARM-technology certified AMBA verification IP. AMBA methodology is the open specification for internal SoC communication. The executable verification plans in the kit are certified for AMBA compliance.
The kit contains block-, chip- and system-level flows and verification methodology tailored for ARM processor designs using the Incisive platform. It also includes applicability consulting and an ARM processor-based representative design. There is also a suite of AMBA methodology-based verification IP, including reusable verification plans, AMBA compliance metrics, advanced testbenches, formal and accelerated protocol assertions, accelerated transactors, processor models and emulation Logic Tiles.
System in Package (SiP) design was also a talking point in Nice, as the increased use of digital architectures, digital signal integrity and digital layout are bringing SiP into mainstream wireless, networking and consumer electronics design projects.
The new RF SiP kit includes new SiP RF products and methodologies from Cadence to automate and accelerate RF SiP design. It focuses on the 802.11 standard with SiP implementation methodologies based on a WLAN design and joins the company’s existing RF Design Methodology Kit for wireless RF design.
The CDNLive! EMEA conference was the first such European event, mirroring the US conference. Although centred around users, it is one level up from a user group, with keynote speeches from Cadence executives, technical panels and seminars and a Designers’ Expo exhibition area. The company plans to introduce CDNLive! into Asia-Pacific regions.
FISTER : holistic advocate
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Cadence lays out
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