What makes a 45nm material world?
01 July 2007
There could be 45nm silicon widely available by the next quarter. CAROLINE HAYES reports on the material changes that will bring this about, from high-k materials to photo mask printing
In quick succession we have seen the progression from 90nm, to 65nm, a brief flirtation with 55nm, before the imminent 45nm process technology. The drive for the smaller geometries is driven by the need for more density, less power consumption and all at a lower manufacturing price per die. As the geometries shrink though, the gate dielectric thicknesses increase as does the rate of gate oxide leakage. Instead high-k materials are replacing silicon dioxide to build transistor gate dieletrics. High-k dielectrics, used with metal gates, improve semiconductor performance while consuming less power.
Companies like Air Products (www.airproducts.com), produces high-k precursors used to deposit defect-free gate dielectrics through chemical vapour deposition or atomic layer deposition. They will be used in logic chips, initially, at the 45nm node, as well as memory chips, where they will be used as stacked capacitors and trench capacitors. Air Products supplies hafnium, zironium, aluminium and lanthanum high-k materials and also provide high-k material etching and formulated cleans to prepare the wafer surface for processing.
Similarly, KLA-Tencor (www.klatencor.com) the process control company has collaborated with manufacturing modelling provider Clear Shape Technologies (www.clearshape.com) to create DFM (design for manufacturing) photomask inspection at 45nm and below. The latter’s modelling techniques use design tolerances from transistor timing analysis to identify areas on the mask that are critical to performance at this mode. The TeraScanHR system uses the information to optimise and enhance the mask inspection parameters on specific, yield-critical photomask features.
Applied Materials (www.appliedmaterials.com) believes it has the only system to deliver the nanomanufacturing technology to etch 45nm photomasks. The Applied Centura Tetra III Advanced Reticle Etch controls trench depths across quartz masks of less than 10A and reduces critical dimension loss to below 10nm for alternating phase shift mask and OPC (optical proximity correction) in critical device layers. The system offers ‘virtually zero-defect’ etch process for chrome, quartz, molybdenum silicon oxynitride (MoSiON) and other new materials for next-gen lithography applications, says the company.
TSMC (www.tsmc.com), the Taiwanese foundry, was the first to announce 45nm readiness, with silicon due in September. It has been collaborating with semiconductor companies and IP vendors in readiness, using its CyberShuttle prototyping programme at the new geometry to deliver two projects already and a further two scheduled for before the year-end.
In the case of TSMC, the 45nm process uses 193nm immersion photolithography, silicon strains and extreme low-k, inter-metal dielectric material. The process delivers a high gate density and high density 6T SRAM cell, with the claim that over 500 million transistors can be accommodated in a 70mm2 die area. The foundry’s Low Power process will be followed by the General Purpose and High Performance processes. There is also a low-power, triple gate oxide option available in the TSMC 45nm logic family. The Low Power, General Purpose and High Performance processes offer a multiple threshold voltage core devices. There are 1.8V, 2.5V, 3.3V I/O options across the process options.
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