Factoring in the power advantages
01 February 2007
FPA 48: 1.2V system with V•I Chips showing available PCB area reduction in input
Today’s high performance computing systems are power-hungry and growing each year. Overall growth in IT demand and increasing energy costs outstrip the improvements in performance per device, resulting in ever higher electricity bills.
The cost of operating power servers will surpass the cost to buy them. As an example of the major steps required to control costs, Google, Yahoo and Microsoft have invested in building new data centres along the Columbia River, NW USA to be as close as possible to ydro-electric power, minimising electrical transition loss and the cost of the electricity.
Traditional ‘AC-to-12V DC Silver Box followed by 12V-to-1.xV synch buck’ designs have run aground in terms of system power density and efficiency due to a combination of distribution bus losses and fundamental restrictions in topology performance as processor voltages reach sub-volt levels. Higher voltage (48V or 350/380V) bus voltages reduce distribution losses but usually mean the addition of an extra stage or stages to get down to the processor voltages which add size and may lower conversion efficiencies. A new solution, factorised power architecture, is required.
This architecture will have to optimise efficiency, thus reducing power costs, while minimising the area used for power delivery in next-generation systems.
In a mid-range/high-end data processing system comprised of one or more blocks of eight microprocessors, each running at 1.2V and 100A for a combine load of 960W per block, efficiency and space comparisons can be made. In this example, the system is fed via an AC-to-48V DC front end from a 208V AC input.
Today’s typical AC-48VDC-1.xV system has an overall 67 per cent efficiency from AC to point-of-load (PoL) which means that for the 960W load, the system draws ~1430W from the AC line. The difference of 470W is lost as heat , further increasing the demands on heat sinking/air conditioning systems and increasing to the running costs of the data centre.
In this analysis, all components/subsystems are considered to be in mass production now with widespread market acceptance and installed base. No ‘exotic’ components / materials are assumed. Topological assumptions are that the AC-48V DC unit comprises a standard bridge, filter and boost power factor correction (PFC) generating 380V and then use a two transistor forward converter with diode rectification to 48V DC. The 48 to 1.2V conversion assumes four 48V:12V unregulated bus converters in quarter-brick format followed by a four- or five-phase VRM/VRD to the processor.
In terms of size, for the front end AC-48V DC, an assumption of 10W/in3 is based on a survey of commercially available units. In typical 800W to 1,500W designs, the PFC stage (including AC-bridge and input EMI filter) occupies around 40 per cent of the whole converter. Typical sizes for the PFC stage and HV (380V to 48V) DC/DC stage were then estimated based on the output power level of each stage. The quarter bricks and VRM/VRO including 'oscon' bulk capacitors dimensions are from specific examples.
Factorized Power Architecture (FPA) FPA uses three flexible building blocks to redefine the boundaries of each conversion stage and enable higher densities and efficiencies. The building blocks (known as V•I Chips) are firstly, the Bus Converter Module (BCM), which is a narrow range input, unregulated, high efficiency bus converter offering isolation and voltage transformation using a ZCS-ZVS sine amplitude converter (SAC). High voltage (up to 384V) and medium voltage (48V) input versions are available.
Secondly, the Pre-Regulator Module (PRM), is a high-efficiency buck-boost converter. Finally, the Voltage Transformation Module (VTM) is a wide range 48V input, high efficiency voltage transformation unit using the ZCS-ZVS SAC and which works in combination with a PRM to give a low voltage output (down to 0.82V as required).
FPA building blocks support greater flexibility, scalability and efficiency in power system design. In terms of size, the SAC in the BCM runs at an effective frequency of 3.5MHz using unique planar magnetics for high power conversion in a small package. This structure results in a power density resulting in power density >1000W/in3. BCMs for DC-DC conversion Upstream, using a PFC front end (e.g. FE375) to create a HV bus and then HV BCM converters create 1,200W at 48V with 95.5 per cent efficiency. This result is included in the size and efficiency summary.
Traditional VRMs/VRDs rely on the tried and trusted synchronous buck PWM converter. However, as processor voltages fall towards 1V and below, the duty cycle from 12V reaches 12:1 (Synch FET: Control FET). Using this PWM topology from 48V in a high power, high efficiency system is challenging due to the extremes of duty cycle coupled with the higher FET voltage requirements and subsequent higher RDS(ON).
FPA enables the separation of the PWM’s regulation and voltage transformation stages into two separate blocks. The PRM generates a factorised bus, controlled to a typical level of 48V, and the VTM (a current multiplier with very low output impedance up to 1MHz) provides high efficiency voltage transformation directly at the processor. For the 960W load, eight VTMs are used (one per 100A processor). As PRM V•I Chips are capable of much higher powers (up to 320W each), only four are needed (in parallel with connected outputs).
FPA delivers high-efficiency and allows power savings upstream. It allows the PRM to be placed at a distance from the VTM, with 94 per cent reduction in distribution losses (W/Ù) at 48V versus a 12V line. It also enables minimal form factor solutions directly at the processor (only the VTM is required to be at the processor to minimise high current traces/losses). High bandwidth bi-directional transformation within the VTM enables the removal of bulk capacitance from the processor location and its replacement by a much smaller (~ 1/1000) capacitance at the factorised bus, resulting in a major reduction in bulk capacitors. Owing to the VTM’s high bandwidth and low Q characteristic, the ceramic bypass capacitor requirement at the PoL is greatly reduced as PoL capacitance is only needed to support dynamic response within a time scale of 1ìsec.
Using V•I Chips to convert the HV DC-DC, MV DC-DC (1/4 brick) and VRMs to an FPA solution means a 8.6 per cent rise in efficiency and a 45 per cent reduction in size versus the original design. However, this result does not include the additional size and efficiency gains from improved connectors and distribution system with FPA.
As well as improving system efficiency and power density, another advantage for FPA using V•I Chips, is the real saving in terms of power drawn from the AC-line. This is the major cost to the user. The 36 per cent lower losses means that the system runs cooler, allowing other components to be more efficient and increasing reliability. It also means that 36 per cent less heat must be removed by air-conditioning, which itself is criticised as inefficient.
Taking into account operating duty cycles and the cost of energy per kWhr, the FPA system saves the end user over $30, £15 or €24 per processor, per year with the added advantage of reducing CO2 emissions.
STEPHEN OLIVER is vice president, V•I chips, Vicor.
Contact Details and Archive...