Foundry business: The ups and downs

01 February 2007

Byers : 65nm low power process has reached maturity
Byers : 65nm low power process has reached maturity

In foundries, the downs refer to the process geometries and the ups refer to the industry prospects, according to Charles Byers, director of worldwide brand management, TSMC (Taiwan Semiconductor Manufacturing Company).

In an interview with Electronic Product Design, Byers shares his views on the technology and the fortunes of foundries and their products.

In the last two calendar years, teh share of sales in 0.5um process technology silicon has remained constant, accounting for six per cent of sales throughout 2006. the older technologies, politely referred to as 'proven', have remained fairly steadfast with 0.25/0.35um accounting for 18 per cent in Q1, 2005 and 13 per cent in Q3 2006. the same holds true, according to TSMC figures for 0.15/0.18um, which remained at around a third of sales in the period, i.e. 31 per cent in Q1 2005 and 33 per cent Q3, 2006. the significant reversal of furtunes belongs to 0.11/0.13um, which fell from 41 per cent in Q1, 2005 to 25 per cent in 2006.

TSMC accounts for a little over 50 per cent of the total market share, estimated to be worth $4.8billion, Q1, 2006. This is shared by Taiwan's UMC at 16.8 per cent, China's SMUC (7.4 per cent) and Taiwan's Chartered Semiconductor Manufacturing (8.1 per cent). Other foundries collectively account for 17.3 per cent of the total market.

The foundry industry collectively faces several challenges, according to Byers. Firstly, the challenge of short lifecycles. A product's lifecycle has shrunk from two years to just one in the space of three generations from 2001 to 2005, he explains.

The growth of the consumer electronics is also a major driver for the shrinking process geometries, which has taken over from the mainframe computers in the 1970s and the PC market in the 1990s. With the proliferation of mobile phones, PDAs and cameras, for example, the industry faces time-to-market, time-to-yield, time-to-ramp (i.e. large scale production), time-to-volume and time-to-money challenges and has to make technology choices. According to Byers, these include the 0.15/0.18um process chioce for SiGe materials and planning for 90nm and 65nm processes for embedded, non-volatile memory and processing to 45nm for embedded DRAM. There are also technolgy choices for high voltage devices, CMOS image sensors adn colour filters, both planned for 90nm.

The next step is 65nm process nodes. Byers believes that TSMC's 65nm low power process technolgy has reached production maturity. There are over 15 customers he says, running production quantities and yields at 65nm. The foundry is currently ramping the node and estimates that by the end of this year, there will be 7,000 to 8,000 12in wafers in production.


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