Design-technology optimisation for 7nm and beyond
11 July 2016
imec partnered with ARM to address the impacts of circuit design and system-level architecture on power, performance, area and cost of nanotechnology chip process nodes.
Luc Van den hove, president and CEO at imec, said collaborating with ARM enables imec’s partners to leverage its process developments to accelerate their design cycle and shorten their time-to-market.
Simon Segars, chief executive officer, ARM, added that advanced process nodes are vital in driving performance and efficiency. Optimising advanced nanotechnology nodes is highly complex and it needs focused expertise to meet challenges in areas such as patterning and power.
A variety of process options can be used to define a technology node, such as the type and number of lithography exposures, the device architecture such as FinFETs or lateral nanowires, the local interconnect scheme, cell architecture and the metallisation scheme. Increasingly, optimising the many choices requires detailed assessment of their interactions with the designs and applications which will utilise the technology.
Initiated in 2009 and now with more than ten international partners, INSITE consolidates the technology knowledge of imec’s logic device scaling program to help companies anticipate new technologies when designing next-generation systems and applications. Studying process assumptions, design targets and trade-offs with expected system performance scaling, INSITE enables strategic product roadmap steering, early feedback toward technology specification, and early decisions on required architectural design changes. This knowledge enables faster learning cycles for technology adoption with reduced risks.
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