Save power and cost with the latest generations of CPLDs

11 December 2015

The architecture of the complex programmable logic device (CPLD) has been through a number of changes in recent years, greatly expanding the range of applications in which this type of component can be put to use and blurring the distinction between CPLD and FPGA.

Yet there are key architectural differences that suit the CPLD-derived devices particularly well to certain uses.

The architecture of the classical CPLD provides a high degree of determinism for logic paths. Each traversal of the logic matrix exhibits the same latency but the global routing architecture becomes prohibitively resource intensive as device sizes increase. In common with the general trend towards very large-scale integration, designers sought higher capacity devices. In order to satisfy this demand, the CPLD vendors introduced a different approach, taking some of the concepts used in FPGAs but reworking them to suit typical CPLD use cases. 

There were two key changes. One was a shift to a distributed routing architecture in which logic paths need not cross the entire chip but can traverse the routes between logic-array blocks that are arranged in a matrix throughout the IC. The second was to replace the product-term arrays with lookup tables (LUT), providing programmable truth tables that operate on four inputs, feeding into a flip-flop.

The more flexible logic architecture of the newer CPLD product families makes it easier to use high-level design languages such as Verilog and VHDL to synthesise logic for the devices. However, the distributed routing fabric can make timing harder to predict for logic designed at the schematic level. The tools for these devices, however, allow a significant degree of control over placement to allow time-sensitive logic paths to be allocated and still be able to employ high-level design techniques, constraints, and definitions to automatically place and route the remainder. In addition, top-level pin planning and locking makes it possible to design the PCB and CPLD logic in parallel, helping to reduce project cycle times.

A key advantage of the CPLD is that it uses non-volatile on-chip memory to store configuration data. The use of on-chip non-volatile memory has two advantages. The first advantage is one of design security. If the device is locked after manufacture to prevent the contents of the configuration being read out, it is much more difficult for a counterfeiter or cloner to determine the structure of the logic held inside. 

The second advantage is that the CPLD is ready to operate at boot time. A number of higher-density CPLDs perform an internal copy from on-chip flash to SRAM-based configuration cells. This approach enables production on conventional CMOS fab processes. The non-volatile memory cells do not need to be distributed throughout the logic array, making it easier to fabricate them. However, even in this case, the configuration time takes a matter of milliseconds and delivers practically instant-on capability in many applications.

The IGLOO2 device made by Microsemi is based on a proprietary process that allows flash memory cells to be embedded in standard CMOS logic. As a result, the configuration is stored within the switch matrix itself, resulting in zero configuration time. This allows the device to be powered down completely during system sleep and avoid the power consumption of reconfiguration when the voltage supply is restored. 

The IGLOO2 devices let the system designer decide whether to retain volatile register and on-chip memory contents, such as data in communications buffers. Retention comes at the cost of some power to maintain the data in suspend latches. Alternatively, the system design may allow the device to be fully powered down and necessary data restored from non-volatile memory following supply restoration.

Lower power consumption for a given logic density compared to FPGAs is another reason why a CPLD-type device can often make a better choice in the context of system design. The ICE40 family from Lattice Semiconductor was designed to support mobile and other low-power designs. The device architecture has features such as programmable low-swing differential I/Os, the ability to turn off on-chip PLLs dynamically and specialised latches that freeze the state of selected inputs to save energy. These features help manage static and dynamic power consumption, resulting in low static power for all members of the family. 

The incorporation of analogue I/O in product families, such as Altera’s Max10, lets the programmable FPGA replace microcontrollers in a number of applications, particularly those that need high-performance real-time processing and highly flexible I/O. The Max10 incorporates a 12-bit, 1Msample/s ADC able to handle up to 17 input channels. 

The high-speed custom logic can also be used to construct analogue I/O functions that can be used for applications such as keypad decoding. For example on an Altera Max device, by adding a low-cost external capacitor it is possible to use an internal oscillator and on-chip Schmitt trigger I/O capabilities to perform analogue-to-digital conversion using a serial converter topology.

Other applications that suit the use of a programmable-logic device over a microcontroller are when there is a need for voltage level conversion between I/Os. This is not easily achieved with a microcontroller because they have a limited number of I/O resources, often operating from one voltage source. In contrast, CPLDs have a larger number of I/Os that are normally grouped into multiple banks. Each I/O bank can be assigned its own voltage source. This reduces the number of components needed to drive common peripherals such as LCDs. 

In addition, the ability to maintain I/Os at low power and perform simple updates make CPLD-type devices highly suitable for energy-sensitive designs that need to continually update LCD status panels and respond to keypad commands. If a microcontroller is still required in the system it can be held in sleep mode for longer. This saves vital power by offloading many functions to the more energy-efficient programmable-logic device.

Another feature that CPLD-type devices have begun to acquire from FPGAs to help them perform embedded processing is arithmetic acceleration. Product families such as the Max10 now offer versions with distributed hardwired multiplier units intended to support high-performance digital signal processing (DSP) functions. In addition, the LUT-based logic blocks of devices such as the ICE40 provide support for carry chains. These support the efficient implementation of adder circuits. 

The combination of arithmetic acceleration and the ability to support high-speed I/O processing suits these programmable-logic parts to applications such as motor control. The logic blocks lend themselves to implementing functions such as pulsewidth modulation (PWM) that are highly instruction-intensive if run in software on a microcontroller. 

Thanks to the addition of modules such as hardware multipliers, the distinction between CPLD and FPGA has become blurred, with a number of former CPLD product families becoming, in effect, non-volatile FPGAs. Yet their features lend themselves to applications that allow them to act as more cost-effective and power-efficient alternatives to both microcontrollers and higher-end FPGAs.

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