PEZY licenses MIPS for “green” supercomputing

17 November 2015

PEZY Computing announces a MIPS64-based PEZY-SC2 family of many-core chips for supercomputers and HPC applications, scaling up to 4096 processing nodes. 

The 64-bit MIPS CPUs will act as the host processors for the system, making PEZY-SC2 the first generation of 64-bit HPC processors from the Japanese company.

MIPS and supercomputers

MIPS has a rich history in HPC applications. Initially used in multiple SGI workstations and desktop computers in the late 1990s and early 2000s, 64-bit MIPS CPUs were later deployed inside several high-profile supercomputers.

Today, high-performance MIPS CPUs can be found in many networking, embedded and desktop SoCs from Cavium, Broadcom, Baikal Electronics and Loongson Technology.

The MIPS architecture provides many great features for HPC applications, including hardware multithreading (up to four threads per CPU), 128-bit SIMD, and full hardware virtualisation (up to 255 guest operating systems). For example, hardware multithreading is very important since many-core chips prefer to use in-order execution cores and rely on multithreading to avoid stalling.

SoC designers can integrate up to 64 clusters of hexacore MIPS I6400 CPUs, each having up to four threads respectively. 

For system architects looking to integrate Out-of-Order 64-bit processors, the recently released MIPS P6600 provides an ideal solution. A high-performance tuned implementation of the Release 6 architecture, MIPS P6600 also includes best-in-class branch prediction and load/store instruction bonding mechanism, two technologies that provide a real boost in single-threaded workloads while keeping silicon area and power consumption in check.


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