Putting the ‘A’ in EDA
06 October 2014
Renowned for its design creation, simulation and verification solutions, EDA company Aldec is celebrating its 30th anniversary, and its three-decade-long journey includes some highly capable responses to genuine industry needs. Moreover, with a claimed user community of more than 35,000 engineers, 50-plus global partners and an impressive product portfolio, Aldec, which remains privately-owned, is clearly doing something right.
Aldec’s founder is Dr. Stanley Hyduke (above) who, in the early 1980s designed his own logic simulator in order to verify the functionality of an ASIC he was developing for a telecommunications application. Impressed by the logic simulator, the foundry with which Dr. Hyduke was dealing at the time urged him to develop it into a commercial product.
Coincidental with the foundry’s recommendation, Dr. Hyduke recognised the huge potential of FPGA technology - very much in its infancy at the time - and the high performance that could be achieved from relatively little engineering effort, certainly when compared to developing an ASIC. He perceived FPGA technology as a real ‘game-changer’, with the potential to serve a variety of new and diverse markets; subject to the availability of appropriate EDA tools and methodologies.
Dr. Hyduke recognised too the importance of the PC and, in particular, Microsoft’s then new ‘multitasking’ operating system, MS-DOS 2.0 (the forerunner of Windows), and the inroads both stood to make into the EDA arena. Meeting these emerging opportunities, along with Dr. Hyduke’s attitude towards R&D and the development of solutions to automate design verification, proved to be foundation of Aldec in 1984.
Aldec’s first official product was launched a year later. It was an MS-DOS-based gate-level simulator called the Standard Universal Simulator for Improved Engineering (SUSIE), the name firmly establishing two of the qualities for which Aldec remains respected today; namely improving engineering productivity and target independence.
Not surprisingly, SUSIE became a popular accompaniment to the vast majority of schematic capture tools of the day. Aldec subsequently ported its simulator to Windows, added schematic entry (at the netlist level) and design management features and rebranded the tool as Active-CAD in 1992.
Though this marked the company’s initial push into the ‘design space’, Active-CAD was a simulator at heart and one of its USPs was its ability to simulate quickly and accurately changes made in the schematic capture part of the tool. This supported not only rapid ‘what-if’ investigations but also ensured there was no disparity between the design (schematic) and early verification results (simulations).
Active-CAD also supported the hardware description languages VHDL and Verilog, though only through macros at the time. Support for HDL-based design entry – for both languages – followed shortly afterwards and the product was renamed Active-HDL, which became, and remains, Aldec’s flagship product for netlist- and HDL-based design and simulation.
Following the introduction of Active-HDL, and in response to industry needs, Aldec turned its attention to other forms of verification. Specifically, as silicon processes improved during the late 1990s, engineers had access to more and more ASIC ‘white space’. However, the engineering effort required to verify the designs filling that space soon became greater than the design effort; and RTL code simulation was taking far too long for designs larger than circa 500k gates.
Also, by the turn of the century, and with the advent of System-on-Chip (SoC) in particular, many designs had become a mixture of hardware IP (existing as VHDL, Verilog or EDIF) and software IP (C, C++ or SystemC), which needed to be verified as one. Accordingly, tackling the ‘verification bottleneck’ and ‘hardware-software co-verification’ were very much the industry’s hottest topics going into the 21st century, and Aldec was quick to respond to both challenges with product offerings.
The first was Riviera-PRO, a VHDL, Verilog, SystemVerilog and SystemC mixed-simulation environment. It built on the simulation capabilities already established within Active-HDL by adding ‘bigger chip’ verification methodologies, such as linting (which has its roots in software design) and functional coverage. Riviera-PRO also supported, and still supports, assertion-based verification, where assertions speed debugging by reducing the number of verification iterations. It also supports team-based design methodologies, as even in the early 2000s it was not uncommon for upwards of 100 engineers to be assigned to an ASIC SoC project.
Aldec’s second solution to early 21st century EDA challenges was its Hardware Emulation Solutions (HES) product. Launched in 2003, HES employs an Incremental Prototyping Technology (IPT) developed by Aldec. It merges RTL simulation with hardware emulation, and verified design sections can reside in hardware (FPGAs) in order to participate in system-level design verification.
HES was very much aimed at accelerating design verification for not only high-density ASICs but also very high gate-count FPGAs as, for example, Xilinx’s claim to delivering industry’s first one-million-gate FPGA had been made a few years earlier, in 1998.
The take up of both Riviera-PRO and HES was extremely encouraging, testimony to how well Aldec had done its market research; and listening to what its customers wanted rather than trying to ‘tell’ them what they should be using.
Another factor was Aldec’s then, and still current, attitude to partnering with IP development companies. One partnership worthy of note here was the addition of Alatek to Aldec’s IP Partner Program in November 1999; and industry pundits of the day were very vocal in commenting on how such partnerships would be essential if engineers were to make efficient use of the growing silicon real-estate that was becoming available thanks to shrinking geometries and yield improvements. Silicon improvements were also pushing FPGA vendors into making even higher gate count and more complex devices.
As mentioned, Aldec’s founder, Dr. Hyduke, recognised in the early 1980s that FPGA technology would be able to serve a variety of market sectors, some of which are heavily regulated by standards to ensure safety. For example, the increased use of FPGAs in the aerospace industry gave rise to the DO-254 standard. It is used to demonstrate the compliance of ‘complex electronics’ – which includes FPGAs, PLDs and ASICS – used in airborne systems.
The standard, which was formally recognised by the Federal Aviation Administration in 2005, requires that designs for safety-critical applications be verified on the ‘real hardware’ as part of the certification process. It also requires that full traceability must exist throughout the entire design flow.
RTL and timing simulations driven by a testbench, and accompanied by code coverage analysis, can ensure 100% coverage of all possible input signal combinations for a design. However, while the simulation results can be easily visualised, analysed, compared and requirements traceability easily maintained, the design behaviour in ‘real hardware’ cannot be easily traced back to simulation.
In response to how increasing numbers of its customers were having to certify their designs against DO-254, Aldec developed a Compliance Tool Set (CTS) for the ‘in-hardware verification’ of designs.
Launched in 2007, Aldec’s DO-254/CTS is a certifiable at-speed FPGA-level in-target testing system; with particular emphasis here placed on both the ‘at speed’ and ‘in target’. Of great benefit is that the CTS automatically generates two sets of test vectors: Golden Vectors, which are the RTL simulation results, used for comparison purposes, and Input Vectors, which are used for the at-speed in-hardware verification. Speed, efficiency and full traceability for certification to DO-254. Once again, Aldec had delivered a solution to meet a genuine industry need.
The successful launch of the CTS, and before that HES which is also an embedded platform for hardware and software co-verification, was very much down to how Aldec keeps product development in-house wherever possible and extremely close collaboration between its hardware and software engineers. The latter point, in particular, is important post-launch of a product; as Aldec says it minimises the number of suppliers and third parties with which the company’s customers may need to liaise if they need support.
Another example of Aldec’s responsiveness to industry needs followed in 2008, with the release of the ALINT design rule checker. Like Riviera-PRO, ALINT is also is a functional verification tool. It reduces verification time by identifying critical issues early in the design flow. Smart design rule checking (using a Phase-Based Linting methodology) points out coding style, functional and structural problems which, if left unchecked, will be extremely difficult to debug in a simulator.
As with Aldec’s other EDA tools, ALINT was welcomed by users, and the addition of a dedicated DO-254 Design Rule Library in 2009 further cemented Aldec’s reputation as not only an EDA company capable of arming engineers with a means of quickly analysing complex designs but also a company very much aligned with the certification requirements of the sectors in which many of its customers work. Not surprisingly, Aldec’s customers today include some of the biggest names in aerospace, defence, automotive, medical and other heavily regulated industries
Languages, Methodology & Training
Aldec supports all leading EDA languages, including VHDL, Verilog, SystemVerilog, PSL and SystemC. Of these the system-level languages are growing in popularity for functional verification. For example, SystemVerilog is at the heart of the Universal Verification Methodology (UVM), an open-source library which allows the creation of verification ‘components’ and the assembly of powerful test environments.
UVM is a popular methodology because its lineage includes the Open Verification Methodology (OVM), which was the first System-Verilog-based verification library available on multiple simulators, and the Verification Methodology Manual (VMM, which harnesses language features like object-oriented programming, randomisation and constraints).
Aldec has supported UVM and its related extensions for a number of years; and about 25% of the company’s users currently subscribe to the methodology. As UVM was gaining in popularity, Aldec noted that many of its customers – predominantly those working in the aerospace and defence sectors (and using VHDL) could also benefit greatly from the advanced verification techniques available within UVM. However, whilst standard VHDL has all the features necessary to code randomisation of stimulus and functional coverage, advanced coding skills are required.
Accordingly, during 2011 and in collaboration with SynthWorks Design Inc., Aldec developed the Open-Source VHDL Verification Methodology (OS-VVM, www.osvvm.org), which includes VHDL packages for Constrained Random Test and Functional Coverage.
The open-source usage model enabled users to get up to speed quickly, and currently about 10% of Aldec’s customers who buy simulator products have adopted OS-VVM. Moreover, Aldec and SynthWorks are developing additional features to further strengthen the methodology as an alternative to UVM.
As mentioned, Aldec supports all leading EDA languages and, while continuing to support VHDL through initiatives like the OS-VVM, a high proportion of the company’s R&D resources are channelled into other system-level languages.
On the hardware front, Aldec’s latest system is the HES-7 (above), a scalable ASIC prototype system that aims to lower the cost of the ASIC prototyping process. The system takes advantage of the Xilinx Virtex-7 2000T 3D IC, which enables design capacity up to 24 million ASIC gates on a single HES-7 board.
HES-7 uses a non-proprietary high-speed backplane connector for the addition of custom daughter boards or for up to four HES-7 boards to be connected together; providing a design capacity of up to 96 million ASIC gates. Since its launch, HES-7 has been adopted by several SoC/ASIC prototyping teams, who have been able to shorten their project lifecycles by not having to partition their designs over large numbers of low density FPGAs.
A company of vision
Aldec has enjoyed an extremely successful and, importantly, very ‘productive’ three decades of EDA business. As a privately-owned company its expansion has perhaps not been at the same pace as some of the larger EDA companies. But one could argue that that is a good thing. Indeed, without the luxury of being able to gamble on future industry developments, Aldec has had to exercise caution throughout its history. Or to put it another way, the company has had to make sure its R&D time was (and continues to be) spent productively; which means listening to what engineers have to say.
Design entry and verification, boosted by considerable levels of automation and methodologies, are of course strong capabilities within the Aldec camp. To a degree though both design entry and verification are just a means to an end, as what the last 30 years have really demonstrated is that Aldec is very adept at visualising design cycles and flows.
Even for large all-code-based designs, graphical representation is essential for architectural exploration; and Aldec’s code-2-graphics engine (present with Active-HDL) has an enviable but justly-deserved reputation within the EDA community. Moreover, the graphical design capability established in Aldec’s early EDA tools has matured into complementary features, such as ‘self-documenting’, within most of the company’s current products and which is very much at the heart of the recently launched Spec-TRACER.
It is a unified requirements lifecycle management solution designed specifically for FPGA and ASIC designs. It helps organisations streamline the requirements engineering process, optimise the development cycle, improve collaboration and (perhaps most importantly) reduce risk and costs.
Spec-TRACER, which integrates with Windows-based HDL design and simulation tools, supports requirements capture and management, change/impact analysis, traceability and reporting. Also, as with all Aldec’s solutions, customers had a say in what Spec-TRACER’s features should be, in order for the tool to be of most use for real-life design flows which, without exception, must accommodate low overall impact rapid changes.
As for the future? Aldec intends to continue to help engineers be more productive; which was very much the goal of Dr. Hyduke in 1984, when he perceived both the opportunities and the challenges associated with emerging technologies.
Moreover, in the same way that Dr. Hyduke built his own simulator back in the early 1980s, there is an admirable ‘can-do’ attitude within Aldec; and products will continue to be developed in-house by engineers who are empathetic to the needs of customers working on projects of varying sizes and which are increasingly for applications within heavily regulated industries.