Closing the gap between design and fab
01 April 2014
Over the years, the IPC have made efforts to fix the disconnect between design and manufacture. This is why the current CID and CID+ programs have an emphasis on DFX.
The thought process here is that, if PCB designers are trained to know the materials, processes, steps and limitations of a PCB fab, then they will inherently know how to design the PCB to be “manufacturable”. Part of this also is the classification of PCBs based on complexity and producibility levels. It counts a lot to actually go to a PCB fab and take a tour. I have done this myself.
I can illustrate the sorts of problems that can occur between design and manufacturing with a tangible real-world example. On a visit to Sierra Circuits in Sunnyvale, I got to walk through the entire process of preparing and laminating a Rigid-Flex panel “book”. It was an eye opening experience - not only for getting to see how a rigid-flex board is made but just as much to be made aware of the fabrication process and its limitations. This was a particularly interesting example, because the PCB in question was very small and had to have thin flexible sections - about 3mm (1/8th inch) in width - between the rigid sections
The big deal with this board was that with such narrow flex-circuit sections, it was not possible to use “bikini” coverlay for the flex. This meant that polyimide coverlay film had to extend through the entire lamination of the board, which in turn meant that acrylic adhesive layers had to be used to adhere the polyimide coverlay layers to the rigid cores. This may not seem like a problem, except that the PCB is 4 layers in the rigid areas, and with such densely populated components on top and bottom layers, the vias were on the risky side of smallness. Why? Because the adhesive layers are known to expand in the z-axis during solder reflow.
In other words, the fab already knew that this board was going to have lowered yields in assembly caused by cracking vias, in turn caused by adhesive expansion, caused by the need to have coverlay film within rigid sections of the board, caused by the size constraints of the design and its mechanical form factor. They actually advised the designer about the problems, and the risk, but the in this case designer was out of time and really could not easily redesign for better assembly yield and maintain the necessary product form factor. This falls into the age-old trade-off between form and manufacturing cost. In this case, the prototypes were needed quickly, so the designer requested production in spite of the associated risk.
Sierra is an example of what I call an educator fab - these are the guys who will tell you what is wrong with your design so that you can try to get it right next time. But there is still a level of frustration that to them, it seems like the designers rarely perform comprehensive DFM checks on their designs. I’m told that it is still most common that designs are at first rejected for DFM issues when the fab runs their own DFM checks using their own CAM/DFM tools.
Another type of fab - such as Hughes in San Marcos California, are just as likely to request the original source documents from the PCB designer in the native CAD format. I refer to these guys as a fix-it fab. You could say part of their service is to make the changes necessary to your design to improve the manufacturing yield and lower costs - optimising your design to their processes and equipment. Most high-volume fabs would want to work with the designer in similar ways to ensure low waste, but if you’re working with fabs on distant shores this may not be desirable. As an example, I asked Hughes about how they need masks to be generated in the CAD software - their response was a solid “don’t, let us do that for you in CAM”.
From all the PCB fabs I’ve talked with, there is an overwhelmingly common message though - even though PCB designers have access to DFM checks and tools, there’s no easy industry standard way for the PCB designer to fully run DFM checks before handoff. This common complaint from the fabs is that designers still largely don’t hand over manufacturing-ready designs.
In response it would be easy to ask what about constraint-driven design? I think that a designer having a good understanding of the constraints and then being able to run Design Rule Checks against the fabrication constraints is an essential part of the solution. The problem with this however is that you often have one design, but multiple fabricators who may use different equipment. Of course, the answer to that problem appears to be well-accepted transfer data formats such as IPC-2581 or ODB++. IPC-2581 has promise for streamlining the data hand-off, but it still doesn’t address the basic problem that, from the outset, designs often begin with too little awareness of how the boards will actually be made once the design is finished.
When discussing these issues, I received a surprisingly overwhelming response that “ECAD tools don’t have proper DFM checks in them”. When I probed deeper, I discovered that the DFM checks referred to are available in the ECAD tool’s Design Rule Check engine – the real problem is actually that the designer either does not apply them, or applies them without properly defining the constraints according to the fab’s capabilities.
Let’s consider silkscreen ink being allowed to print over bare copper. As a test, I sent a design which had a small bit of silkscreen designator text over an untented via to three different fabs. An educator fab, a fix-it fab, and a broker for offshore fabs. The educator fab immediately informed me that I had silkscreen over a mask opening and it had to be fixed in my design. The fix-it fab asked for the files in the native (Altium Designer or Protel) format, and the broker simply sent the gerbers to a fab which eventually emailed me informing me that some silkscreen items would be removed because of overlap with mask openings. In all three cases, at a minimum the production date would be delayed. So what are the options for a solution?
One option is to develop some standard basic DFM checks which all designers can handle for simple to moderate (Level 1 and 2 producibility) designs. In this case, an industry body could publish a list of DFM checks and their tolerances which could easily be ported into any ECAD design rule check engine, so designers could efficiently apply them and have confidence that most fabs would successfully produce the boards. This sounds good, but it’s actually quite a difficult thing to achieve – the number of constraints that would have to be thought of ahead of time is staggering.
Another option is for the fabricators to be more involved in ECAD tool development. While some have actually used free PCB design tools as a loss leader, it is a very difficult thing to make tools which can handle cutting edge or even some mainstream designs efficiently.
A better solution space for this problem is for fabricators to have technical staff actually involved in design planning and in setting up the rules and constraints as early as possible in the design process. The difficulty on the face of this solution is that you may have to know up front who your fab is. Most companies tend to use the same fabs over the long haul so it’s not such a big deal. This can be further eased by the fabs. I think the fabs have a great opportunity to improve business here and I can see at least a few ways of making this easy for designers to really get it right the first time:
? At the simplest level, the fabs need to get into each ECAD toolset, and produce a pre-packaged set of DFM rules (or constraints) for each production line or process complexity level they support. Then, those DFM rule sets can be published or made as a download from the web for the customers who are working with that fab. In turn, the designer can then run a DFM check which gives a high confidence when everything passes, that the fab they are using will be able to get good yields with their design.
? Going a step further, PCB fabs could offer whole template projects for various toolsets as free downloads for their registered customers, which in a “shrink wrap” include the various DFM checks for their production lines.
? Take this one step further again: ECAD tool vendors like Altium, could make the API for the software available to the fab who can build their own quoting and DFM check systems into the ECAD tool, so the designer who intends to use that fab can make sure their design is good with the click of a button, and even receive a quote from the fab for prototyping.
There’s a lot that can be done here. The third solution requires the fabricator to have the necessary software infrastructure in place and secure links between ECAD and online DFM servers. However it adds two distinct advantages. The first is that the PCB fabricator can run full DFM without exposure of their processes, and the other is that the designer can run DFM checks against a real fab’s processes without other humans interacting with their design source documents.
For these problems to be solved in a way that best suits the designer, integration is really needed. Closing the gap between design and fabrication needs reliable and universal data transfer, yes, but it needs above all, good collaboration between all parties involved. Having good file formats is important, but it is not the complete solution. While work has been done with ODB++ and IPC-2581, the uptake is slow - ODB++ has less than 20% use according to the fabs, and IPC-2581 is in its infancy.
Figure 1: Difficult-to-make rigid-flex board.
Figure 2: White acrylic adhesive layers are added to the lamination book.
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