Serial Interface for data converters
06 August 2008
Spectrum analysers can improve overall system performance with the capability to isolate the digital and analogue circuitry
The benefit of the parallel interface is its simple receiver design. However, it requires a large number of pins on the transmitting and receiving devices. Single-ended CMOS outputs have a 1:1 ratio of bits to output pins. Therefore, a 16bit ADC needs 16 digital output pins.
Linear Technology ADCs have the capability to power the digital output supply as low as 0.5V when using CMOS outputs.
Parallel LVDS interfaces offer small signal swings and may be capable of operating at speeds as high as 1.7Gbyte/sec, although the difficulty of capturing the data stream and maintaining BER (bit error rates) make the practical transmission speeds closer to 1Gbyte/sec. The main disadvantage of parallel LVDS is the need for two lines for every bit on the data converter output.
An alternative to parallel LVDS is the LVDS serial CDF (clock-data-frame) interfaces, where a serial LVDS data stream is transmitted alongside separate differential frame and bit clocks. Standard implementations are limited to data rates of less than 1.2Gbyte/sec due to the limitations of the DLL (delay lock loop) in the
transmitter to align the frame, clock and data.
At higher bit rates, controlling possible skew between the output clock and data stream makes this type of interface difficult to manage. For ADCs that sample above 14bit and 65Msample/sec, the data must be separated (or demultiplexed) into two LVDS pairs and clocked at half the rate of the single data line. This method requires a minimum of eight wires; two data pairs along with an LVDS pair for both the frame and clock.
Serialised LVDS helps to simplify routing between the ADC and processor, along with reducing output switching noise that can couple back into the analogue input. It is more popular in multichannel applications such as ultrasound, where multiple ADCs are integrated into a single package.
Another method for reducing the number of wires required to transmit parallel data is DDR (double data rate) transfer, where the two bits of data are transmitted on a single wire (DDR CMOS) or on an LVDS pair and clocked on both edges of the output clock.
A new serial interface standard
In April 2006, the JEDEC group formulated a serial interface specification (JESD204) that enables a high-speed serial connection between data converters and logic devices over two-wires. The electrical layer of the
specification supports code rates of 312.5Mbyte/sec to 3.125Gbyte/sec across a CML (current mode logic) pair. The selfclocked serial data stream is encoded using 8B/10B coding, developed in the early 80s by IBM. It uses a running disparity to eliminate DC imbalance in the signal.
Limited run length, a limit in the number of successive ones or zeros, allows the decoder to extract the clock from the data. The encoder keeps track of the number of ones and zeros that have been transmitted in each data set and the encoder will then encode subsequent data to eliminate the DC imbalance. In the case where there are an equal number of ones and zeros in a data frame, the running disparity remains unchanged. By not having a DC offset, the signal can be transmitted through high pass elements such as transformers or optical receivers. The self-clocking feature eliminates the need to send a synchronous
clock along with the data stream. Special characters denominated as comma symbols are used to align the receiver to the correct boundaries and rates, and then the receiver can maintain those conditions to collect the subsequent data. Once sync is established there may be no need to introduce more commas in the data stream unless sync is lost, however it may be desirable to periodically check synchronisation of data. If
the receiver requests a synchronisation pattern from the transmitter, (the ADC), there would be a loss of data associated the synchronisation event. To avoid this loss, the JESD204 specification calls for a FAM
(frame alignment monitoring) mode which allows synchronisation to be checked without losing data, or asserting the sync pin on the transmitter.
In contrast to a parallel interface ADC that requires 16 CMOS or 32 LVDS digital lines to interface a 16bit ADC to an FPGA/ASIC, this JEDEC defined serial interface requires only two.
The high-speed serial interface enables two-wire communication between the data converter and a dedicated SerDes port on the FPGA. This frees up FPGA general purpose I/O pins for other uses, or allows
designers to purchase a smaller FPGA with fewer I/O pins. In addition, routing 16 or 32 digital I/O lines requires attention to layout to avoid digital feedback. Parallel interfaces use board real estate which makes it more difficult to separate the sensitive analogue circuitry from the digital circuitry, so a simplified layout is beneficial. Furthermore, in noise-sensitive applications this serial interface can be transmitted across an
isolation barrier between digital and analogue circuitry, and serves to eliminate digital feedback.
Previously, a system with four 16bit ADCs with parallel LVDS outputs would need to route 128 digital output lines between the ADC and the FPGA. Even with a quad ADC, the current serial LVDS interfaces require
16 LVDS data lines, plus an additional four lines of clock overhead. In contrast, for the JEDEC serial interface only eight high speed digital output lines would be routed between four ADCs and the FPGA.
Linear Technology’s LTC2274 is a 16bit, 105Msample/sec serial ADC with a data output rate of 2.1Gbyte/sec. The 16bit data word is divided into two 8bit octets and then each are transmitted as a 10bit code group with bounded disparity. This means 20 CLKOUT cycles are required for a full data transfer. The JEDEC serial interface is compatible with many FPGA high speed interfaces including Xilinx’s Rocket IO,
Altera’s Stratix II GX I/O and Lattice’s ECP2M I/O, and reference designs using the LTC2274 are available from each of these FPGA manufacturers.
One of the biggest challenges in the design of these new converters was achieving the high AC specifications while integrating the high-speed serial interface on the same die. The LTC2274 has a SNR (signal to noise ratio) performance of 77.5dBFS (decibels relative to full-scale) and SFDR (spurious free
dynamic range) of 100dB at baseband. These AC specifications enable low-level signals to be resolved in the presence of large interferers or blockers, which is especially critical for multi-channel receiver
applications. Ultra low internal jitter of 80fsRMS enables under sampling of input frequencies up to 500MHz while maintaining good noise performance, allowing the ADC to sample closer to the antenna. The LTC2274 draws 1.3W from a single 3.3V analogue supply and is provided in a 6mm x 6mm QFN package.
The LTC2274 has an internal transparent dither circuit, which solves the problem caused by sampling low level input signals.
Small signals well below the full scale input of the ADC only exercise a small region of the ADC transfer curve, where only a small number of output codes are repeated. Even slight non-linearities in the transfer curve will cause harmonic distortion in the output spectrum, which degrades SFDR performance (see figure 3a). By adding a small amount of dither into the ADC pipeline, a wider range of the transfer curve is used
and the probability of operating on a nonlinear region is reduced (see figure 3b). Before the digital output is transmitted, the dither signal is subtracted from the output, resulting in a large improvement in SFDR for a small trade-off in noise; a feature particularly important for high sensitivity receivers.
The JESD204 specification also calls out an optional data scrambler that scrambles the data before it is encoded for transmission. This helps to avoid unwanted spectral components that can occur with high-speed serial transmission. By scrambling the data, the octets that are encoded are data independent,
which will eliminate spectral artefacts that can occur with certain data dependant signals. The polynomial and scrambling scheme can be used with a selfsynchronous descrambler. The FPGA must have a descrambling algorithm to descramble the data after the 8B/10B decoder. Serial test patterns are also
available to facilitate testing of the serial interface and verify BER.
High performance communications equipment such as basestation receivers and digital pre-distortion transmitters can achieve cost savings using the dedicated SerDes port on the FPGA, while benefiting from the high SNR and SFDR performance for multi-carrier receiver designs. Spectrum analysers can improve overall system performance with the capability to isolate the digital and analogue circuitry, whereas
multichannel applications such as ATE and medical imaging will appreciate the reduced pin count for ease of routing and additional space savings.
ALISON STEER is product marketing manager, Linear Technology
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