Driving displays both big and small

Author : Stefan Drouzas, Toshiba Electronics Europe

27 June 2016

Figure 1 - Data compression typically requires multiple encode/decode operations on pixel data.

The ever-increasing diversity of mobile devices and end-user demands is driving designers to develop flexible ways of displaying high-definition content across a wide range of screen types and sizes.

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Smartphones, tablets and emerging categories of devices such as smart watches and 4K Ultra HD televisions are the shining stars of the consumer electronics industry, sustaining markets worth hundreds of billions of dollars globally according to industry bodies such as the US Consumer Electronics Association (CEA). For each new device brought to market, screen performance is a key factor that determines the quality of the user experience. Quite apart from battery life and execution performance, creating a good visual impression is vital for sales success.

Users expect to enjoy sharp, vibrant, high-definition images and video from the Internet, social media or on-board HD camera. Users also increasingly expect to be able to share content easily between various devices regardless of differences in screen type, such as viewing video originally shot on a smartphone in crystal-clear HD on a large PC monitor or flat-panel TV.

Figure 2 - Simplified pixel-data transfer with DSC included in DSI interface specification.

Resolution, memory and power

Satisfying such high expectations requires careful engineering of the display link connecting the host system to the display panel. High display resolutions and screen refresh rates, which are needed to deliver maximum image quality and sharp video, place upward pressure on interface data rates leading to higher system power consumption. This, of course, is the archenemy of the mobile device designer. Long battery lifetime, minimal weight and a stylish compact form factor are equally as important to users as image quality and video performance. 

As far as smartphones are concerned, display resolution has been increasing faster than 200% per year, significantly outstripping increases in the per-lane bit rate of physical interfaces. Display data rates in televisions are also increasing aggressively: a 1080p high-definition television display requires a video data rate of 3.5 Gbps, while a 60Hz 4K UHD display requires 14 Gbps. In the future, next-generation 8K displays will require bandwidth of over 50 Gbps.

Figure 3 - High-level block diagram for popular small tablet with retina-resolution display.

Compressing the pixel data using a visually lossless compression algorithm potentially offers a solution. A number of video compression standards have been published, aimed at various applications, which help to reduce pixel-data rates thereby easing pressure on link bandwidth and system power. Compression also alleviates storage requirements thereby helping to save system cost.

Typically, if compression is applied, the pixel data has to be encoded and decoded several times between the input to the host system and the output to the display. As Figure 1 illustrates, the data is encoded for storage by the host system, and is then decoded prior to transmission via the interface to the display module. Subsequently, the data is re-encoded into the display module buffer before being finally decoded into a suitable format for the display.

Tackling the bandwidth challenge

Figure 4 - DSI to eDP bridge for tablet applications.

Among compression standards suitable for host-to-display transmission, the VESA (Video Electronics Standards Association) Display Stream Compression (DSC) standard is currently adopted both in VESA’s embedded DisplayPort (eDP) v1.4 and the MIPI Display Serial Interface (DSI) Specification v1.2. DSC can reduce pixel data rates by up to 66%, delivering a valuable saving in system power demand. Moreover, the compression algorithm is simpler than other transform-based algorithms resulting in lower latency and lower use of memory resources. DSC can support a wide range of display resolutions, from the types of panels used in entry-level smartphones, to 4K Ultra HD televisions and forthcoming 8K equipment.

Both eDP and DSI are commonly used for embedded display interfaces within mobile systems, including smartphones, tablets and laptops. Both standards help to enhance interoperability between host processor and display products from different vendors. Exchanging pixel data compressed using DSC across the DSI 1.2 interface is significantly simplified compared to approaches using alternative compression algorithms. As Figure 2 shows, the need to decode the data for transmission over the DSI 1.2 interface, and subsequent re-encoding in the display module, are eliminated.

Despite the compelling arguments in favour of a standardised display interface, the chosen application processor for a given new product design may not support DSI, or in some cases does not provide enough DSI lanes to connect directly to a favoured off-the-shelf display module. In such cases, a bridge IC is needed to interface the video output of the application processor to the input of the display module. Toshiba has implemented a number of bridge ICs that give developers extra flexibility to connect a wide variety of application processors to currently popular screen sizes and resolutions using a standardised MIPI DSI or VESA eDP interface. These are applicable to various high-volume consumer products such as smart watches, standard or mini-sized tablets, all the way up to 4K UHD screens.

Figure 5 - Smart watch application, connecting DSI-enabled host processor to QVGA or similar resolution RGB display.

Figure 3 shows the example of a mini tablet device featuring a high-quality 720p display that requires a 4-lane MIPI connection. Unfortunately, the candidate application processors best suited to this application support only one dual-lane DSI output at best. Using a bridge IC such as the Toshiba TC358768 or TC358778 allows the pixel data at the host RGB interface to be converted to MIPI DSI in 4-lane video mode at 1Gbps per lane.

Other types of tablets may use a screen supporting the VESA eDP interface. If the chosen host processor does not support eDP natively, a bridge such as the TC358770/7 can be used to convert video from DSI format to eDP as shown in Figure 4.

In an application with a small display, such as a smart watch, the typical challenge facing designers is to connect a host processor with DSI interface to the small display that typically has a parallel RGB input. In this case, the TC358762 provides a suitable DSI-to-RGB bridge, as Figure 5 illustrates.

Figure 6 - A mobile application processor can power 4K-ready devices using an HDMI to dual-CSI bridge.

Connecting HDMI sources

Not satisfied with enjoying great viewing experiences on the go, mobile users also want to stream content easily between devices with complete flexibility to transfer video from any source to any display on any kind of device. This may be sending full-HD video originally captured on a mobile to view on a large flat-panel TV screen, or alternatively connecting any source to a mobile device. 

An HDMI source with up to 4K resolution can be connected to any application processor featuring a dual MIPI Camera Serial Interface (CSI) using the TC358840 HDMI to Dual CSI2 bridge shown in Figure 6. By making the Ultra HD HDMI interface look like a camera interface, this device opens up 4K video opportunities to devices based on smartphone application processors, and can also be used to create digital media adapters.

Combining a suitable bridge with a wireless-enabled application processor, as shown in Figure 7, enables streaming of full-HD video from an HDMI source to a smart monitor, flat-panel television or smart TV. A reference design and evaluation board featuring the TC358743 HDMI-CSI2 bridge IC and TZ5000 wireless application processor gives designers a head start creating a wireless HDMI dongle for maximum convenience and freedom.

Figure 7 - Wireless option for HDMI to FPTV or monitor.

Conclusion

MIPI standards have opened interoperability and DSI has been adopted in leading application processors for smart watch, tablet, and smartphone. That sector continues to evolve, however, and engineers need suitable solutions for cases where the application processor may not support DSI or insufficient DSI lanes may be available. On the other hand, many displays still commonly used in mobile and portable devices do not support DSI and may instead have a parallel RGB interface.

Bridge ICs enable designers to maximise the advantages of DSI in new designs, taking advantage of industry-standard DSC compression to minimise pressure on pixel data rates, system power consumption and bill of materials costs. These ICs can help today’s smartphone owners enjoy their mobile lifestyles to the full. 


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